第一顆電路為內具線性器之28 GHz二級功率放大器，透過傳輸線匹配網路達成輸出功率阻抗匹配、輸入共軛匹配之效果。當VG = 0.5 V時，且線性器為關閉狀態(Vctrl = 0 V)時，在頻率為28 GHz下，其功率增益(Power gain)約為21.16 dB，飽和輸出功率Psat約為24.63 dBm，1-dB增益壓縮點之輸出功率(OP1dB)約為24.01 dBm，最大功率附加效率Peak PAE約為36.41 %，而當線性器為開啟狀態((Vctrl1 = 0.35 V、Vctrl2 = 0.15 V)且頻率為28 GHz時，IMD3在-40 dBc時的輸出功率為16 dBm，整體晶片佈局面積為1 mm × 2 mm。
第二顆電路為28 GHz PIN二極體切換器，採用四分之一波長線的SPDT架構。當操作頻率為28 GHz且VON為-4 V、VOFF為1.3 V時， 插入損耗約為2.15 dB，輸入輸出反射損耗(S11、S22)分別為14.07 dB與9.92 dB，0.1-dB增益壓縮點之輸入功率(IP0.1dB)約為17 dBm，整體晶片佈局面積為1 mm × 1 mm。

First, 28 GHz two-stage power amplifier with a built-in linearizer achieves output power matching and input conjugate matching through a transmission line matching network. When VG = 0.5 V and the linearizer is off (Vctrl = 0 V), the power gain at 28 GHz is 21.16 dB, the saturated output power (Psat) is 24.63 dBm, the output power at 1-dB gain compression point (OP1-dB) is 24.01 dBm, and the maximum power added efficiency (PAE) is 36.41 %. Moreover, when the linearizer is on (Vctrl1 = 0.35 V, Vctrl2 = 0.15 V) and the frequency is 28 GHz, the output power of IMD3 is 16 dBm at -40 dBc and the chip size is 1 mm × 2 mm.
Second, a 28 GHz PIN diode switch adopts SPDT architecture with quarter wavelength lines. When operating at 28 GHz with VON at -4 V and VOFF at 1.3 V, the insertion loss is 2.15 dB, the input and output reflection losses (S11 and S22) are 14.07 dB and 9.92 dB respectively, and the input power at the 0.1-dB gain compression point (IP0.1dB) is 17 dBm, and the chip size is 1 mm × 1 mm.

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