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研究生： 謝侑霖
You-Lin Sie
論文名稱： 基於渾沌門檻值調變與邊緣增強誤差擴散法之FPGA設計與實現
Design and Implementation of Chaotic Threshold Modulation and Edge Enhanced Error Diffusion on FPGA Chip
指導教授： 蘇崇彥
Su, Chung-Yen
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 95
中文關鍵詞： 誤差擴散法 、數位半色調 、FPGA
英文關鍵詞： Error Diffusion, Digital Halftoning, FPGA
論文種類： 學術論文
相關次數： 點閱：131  下載：2 
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    • 數位半色調是一種將連續色調影像轉換成有限色調影像的技術，此技術的主要特點為使用有限的色調去呈現出連續色調的影像。此特點被廣泛應用於顯示器與印表機裝置上。然而，傳統的數位半色調演算法仍有一些缺點，因此在本論文中我們提出一個新的數位半色調演算法。有別於傳統演算法使用固定的門檻值，我們的演算法所使用的是渾沌門檻值調變，藉由渾沌門檻值調變去減少圖片中不自然的紋理。為了更進一步的增加圖片的視覺品質，我們加入邊緣增強之量化方式以增強物體之邊緣。最後為了增加執行速度以符合即時處理之需求，我們設計了一個硬體電路來實現我們的演算法。實驗結果證明，我們所提出的新演算法的確能提高視覺品質，得到較佳的圖片，並且我們設計的硬體電路的執行速度能比軟體的執行速度快超過10倍。

    Digital halftoning is the technique of transforming continuous-tone images into a limited number of gray level ones. The goal is to create the perception of a continuous-tone image using limited gray levels. Hence, it is broadly applied to display and printing devices. However, there are still some problems in traditional digital halftoning methods. In this thesis, we present an effective digital halftoning algorithm to solve these problems. Unlike traditional algorithms using the fixed threshold, the new algorithm uses chaotic threshold modulation to reduce the visual artifacts. Furthermore, for edge enhancement, we also incorporate a novel quantization method into our algorithm. To speed up the execution time to meet the requirement for real time processing, we design a useful hardware architecture to implement the proposed algorithm. In our experiment, the proposed algorithm achieves more satisfying performance than existing algorithms and the execution time of hardware can be sped up more than 10 times than software.

    摘 要 i ABSTRACT ii 致謝 iii Contents iv List of Figure vi List of Tables x Chapter 1 Introduction 1 1.1 Background of Research 1 1.2 Design Motivation and Purpose of Research 3 1.3 Thesis Organization 4 Chapter 2 Overview of Digital Halftoning 5 2.1 Overview 5 2.2 Point-Process Algorithms 8 2.2.1 Threshold Dither 8 2.2.2 Bayer Dither 10 2.3 Neighborhood-Process Algorithms 14 2.3.1 Conventional Algorithms 14 2.3.2 Probabilistic Error Diffusion for Image Enhancement 19 2.3.3 Edge-Directed Error Diffusion Halftoning 23 2.3.4 Error-Diffusion Algorithm with Edge Enhancement 26 2.4 Summary 27 Chapter 3 Chaotic Threshold Modulation and Edge Enhanced Error Diffusion 29 3.1 Overview 29 3.2 Proposed Algorithm 31 3.2.1 Gradient-Based Edge Detection 32 3.2.2 Chaotic Threshold Generation 34 3.2.3 Edge Enhanced Quantization 37 3.2.4 Error Diffusion 38 3.3 Summary 39 Chapter 4 Hardware Implementation 40 4.1 Overview 40 4.2 FPGA Solution 40 4.3 Hardware Platform Diagram 41 4.4 Design Flow 42 4.5 Hardware Design and Implementation 43 4.5.1 Edge Detection Circuit 44 4.5.2 Chaotic Threshold Generation Circuit 45 4.5.3 Edge Enhanced Quantization Circuit 48 4.5.4 Error Diffusion Circuit 50 4.5.5 Data Transmission Circuit 51 4.6 FPGA Verification 53 4.7 Summary 54 Chapter 5 Simulation Results and Performance Comparisons 55 5.1 Overview 55 5.2 Simulation Results Based on Software 55 5.3 Simulation Results Based on Hardware 71 5.4 Software vs Hardware 78 5.5 Experimental Results of EPD 79 5.6 Edge-Enhanced Measurement 80 5.7 Summary 81 Chapter 6 Conclusion and Future Work 82 6.1 Conclusion 82 6.2 Future Work 82 References 84 Appendix 1 88 Appendix 2 93

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