研究生: |
李洹 Huan Lee |
---|---|
論文名稱: |
氧化釔閘極介電層之電性與漏電流機制研究 Electrical Properties and Leakage Current Mechanism of Y2O3 Gate Dielectrics |
指導教授: |
劉傳璽
Liu, Chuan-Hsi 程金保 Cheng, Ching-Pao |
學位類別: |
碩士 Master |
系所名稱: |
機電工程學系 Department of Mechatronic Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 94 |
中文關鍵詞: | 氧化釔 、鋁 、濺鍍 |
英文關鍵詞: | Y2O3, Al, sputter |
論文種類: | 學術論文 |
相關次數: | 點閱:180 下載:0 |
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本實驗之中,我們成功地製作了Al/Y2O3/p-Si的MOS電容器,我們使用射頻濺鍍法沉積Y2O3薄膜其厚度為7 nm,沉積完後再分別做650、750和850 oC的快速熱退火,最後再沉積Al當作電極。由X-ray繞射儀的分析比較不同退火溫度下的Y2O3薄膜,發現在做完850 oC的快速熱退火之後Y2O3薄膜沒有結晶的產生,顯示Y2O3這個材料有很高的結晶溫度,並且隨著退火溫度的增加在2θ=55o的峰值也跟著上升,其中55o的峰值指的是矽的金屬氧化物。接著利用X-ray光電子能譜儀進行成份的分析,由分析的結果得知的確有矽的金屬氧化物的存在,並且隨著退火溫度的上升,矽的金屬氧化物的含量也是有增加的。
接下來則是對Y2O3薄膜進行C-V和I-V的量測,首先是C-V量測的結果,隨著退火溫度的上升所量測到的電容值會降低,計算得到的介電常數也跟著下降。其原因是因為由於有矽的金屬氧化物的產生,而矽的金屬氧化物本身的介電常數較低,所以有矽的金屬氧化物的產生會造成整體的介電常數下降。另外I-V的量測結果則顯示,隨著退火溫度的上升所量測到的漏電流會降低,其退火溫度為650和850 oC所量測到的電流值分別為4.56×10-1 A/cm2和3.43×10-2 A/cm2。而原因可能是因為有矽的金屬氧化物的產生,而造成整體的厚度增加使得漏電流下降。
Ultra-thin yttrium oxide (Y2O3) films were deposited on p-Si(100) substrates by RF sputtering in argon (Ar) ambient at room temperature. The physical thickness of the films was around 7 nm. After deposition, a post-deposition annealing (PDA) in nitrogen (N2) ambient was then performed from 650 to 850 oC. The chemical bonding states and depth profiles of the films were characterized by X-ray photoelectron spectroscopy (XPS) and X-ray reflectivity (XRR),respectively. The crystalline phase of the films was analyzed by X-ray diffraction (XRD). For electrical characterization, aluminum (Al) was deposited as the gate electrode to form the MOS structure. Electrical characterization consisted of high frequency C-V(capacitance-voltage) and J-V (current density-voltage) measurements. According to the XRD patterns, Y2O3 films emain amorphous after 850 oC annealing. Moreover, also confirmed by XPS results, the formation of yttrium silicates (YSiOx) was observed after 650 oC annealing, and the silicate thickness increases with the annealing temperature. It is also suggested that the interfacial layer YSiOx dominates the gate leakage current of the MOS capacitors. As a result, unlike most of the high-κ gate insulators, the gate leakage current density decreases from 4.56×10-1 A/cm2 to 3.43×10-2 A/cm2 at Vg = -2.5 V as the annealing temperature increases from 650 to 850 oC.
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