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研究生: 黃易寒
Yi-Han Huang
論文名稱: 利用田口法優化高介電係數鋁氧化鉿薄膜特性
The Optimization of Film Characteristics of High-K HfAlO Dielectrics Using Taguchi Method
指導教授: 王偉彥
Wang, Wen-Yen
劉傳璽
Liu, Chuan-Hsi
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 74
中文關鍵詞: 田口法氧化鉿鋁高介電係數薄膜
英文關鍵詞: Taguchi method, HfAlO, High-k thin films
論文種類: 學術論文
相關次數: 點閱:180下載:9
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  • 本研究主要是將田口法應用在尋找高介電係數薄膜鋁氧化鉿之優化參數配方。 氧化鉿高介電係材料其結晶溫度過低,大幅降低於實務運用上之可能性,所以透過摻雜鋁提升結晶溫度並於XRD中證明其是有效的。首先適當選擇對薄膜品質特性之影響因子與變動水準,再藉由田口直交表所安排之參數配方製作以鋁氧化鉿薄膜為基礎之鋁/鋁氧化鉿/P型矽基板結構之電容器,量測其電壓-電流與電壓-電容特性曲線,並將針對不同之品質特性,使用適當之訊雜比公式,依據其所計算之數值選取每個變動因子之最佳水準數。
    再將所選取之優化配方與田口直交表內所有配方做比較,經過電壓-電流特性曲線、電壓-電容特性曲線、XRR、AFM的量測分析,證實利用田口法所尋找之優化配方在漏電流或是電容值方面的品質特性比傳統實驗設計法更有效率且也確保了優化的精準性。

    The purpose of this study is to apply Taguchi method for recipe optimization of high-k HfAlO thin-films. It is known that the crystallization temperature of HfO2 thin-films is relatively low and this limits the applications of HfO2 thin-films. In this study, aluminum has been doped in HfO2 films to raise the crystallization temperature, which was verified by XRD. First, the effect factors and their levels with regard to the film characteristics were selected. Then the MOS capacitors (Al/HfAlO/p-Si) were manufactured according to the Taguchi orthogonal array (OA). Finally, I-V (current-voltage) and C-V (capacitance-voltage) measurements were made and evaluated. Based on the electrical measurements, signal/noise (S/N) ratios were calculated the optimal level of each factor was accordingly selected.
    In order to verify the validity of this method, I-V, C-V, XRR, and AFM characteristics of the resultant recipe (i.e. combination of optimal levels of all factors) were also compared with those of the recipes shown on Taguchi orthogonal array. Based on the results of this study, it can be concluded that the capacitance and leakage characteristics of high-k thin-films can be significantly improved through Taguchi method efficiently.

    中文摘要 i 英文摘要 ii 誌謝 iii 目錄 iv 圖目錄 vii 表目錄 x 第一章 緒論 1 1.1 研究背景與動機目的 1 1.2 本論文研究方向 2 第二章 文獻探討 3 2.1 田口法 3 2.1.1實驗設計法 3 2.1.2 田口法概念 7 2.1.3 品質損失函數 11 2.1.4 訊雜比 14 2.2 金氧半場效電晶體 15 2.2.1金氧半場效電晶體結構與運作原理 15 2.2.2金氧半電容器結構與運作理原 18 2.2.3金氧半電容器非理想閘極氧化層 20 2.2.4金氧半電容器漏電流機制 23 2.3 高介電係數金氧半電容器 28 2.3.1高介電係數 29 2.3.2 高介電係數材料 29 第三章 實驗設計 36 3.1 田口法優化氧化鉿鋁及其製備相關介紹 36 3.2 薄膜物理特性量測設備與其運作原理 44 3.2.1 X光繞射儀 45 3.2.2 X反射率儀 46 3.2.3 橢圓儀 46 3.2.4 I-V與C-V電性量測 47 3.2.5 原子力顯微鏡 47 第四章 結果與討論 48 4.1 田口法分析HfAlO薄膜品質特性 48 4.2 從電性與物理量測證實田口法優化結果 49 第五章 結論與未來展望 67 5.1 田口法優化Al/HfAlO/Si電容器品質特性 67 5.2 未來展望 67 參考文獻 69 自傳 73 學術成就 74

    [1] G. Taguchi, “Taguchi methods in LSI fabrication process”, proceedings of IEEE International Workshop on Statistical Methodology, 2001. pp.1-6.
    [2] D. Clausing, “Taguchi methods to improve the development process”, Proceedings of IEEE International Conference on Communications, 1988, pp.826-832.
    [3] 李輝煌,”田口方法品質設計的原理與實務”,高立圖書有限公司出版, 2011.
    [4] S. Stoica, “Robust test methods applied to functional design verification”, Proceedings of the International Test Conference, 2008, pp. 848 –857.
    [5] M. Severgnini, L. Pattini, C. Consolandi, E. Rizzi, C. Battaglia, G. D. Bellis, and S. Cerutti, “Application of the Taguchi method to the analysis of the deposition step in microarray production”, Journal of IEEE Transactions on NanoBioscience, vol. 5, pp. 164 –172, 2006.
    [6] T. Cahyadi, P. Y. Tan, M. T. Ng, T. Yeo, J. J. Boh, and B. Fun, “The use of Taguchi method for process design of experiment to resolve gate oxide integrity issue”, Proceedings of IEEE International Integrated Reliability Workshop, pp. 128 – 131, 2009.
    [7] J. Bardeen and W. H. Brattrain, “A semi-conductor triode”, Physical Review 74, 230, 1948.
    [8] W. Shockley, “The theory of p-n junction in semiconductors and p-n junction transistors”, Bell System Technical Journal 28, 435, 1949.
    [9] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, New York , 2007.
    [10] W. G. Pfann and C. G. B. Garrett, “Semiconductor varactors using surface space-charge layers”, Proc. IRE 47, 2011, 1959.
    [11] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, New York, 2007.
    [12] 劉傳璽、陳進來,”半導體物理元件與製程-理論與實務”,五南文化出版社,2006.
    [13] B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, “Characteristics of the surface-state charge of thermally oxidized silicon”, Journal of The Electrochemical Society 114, 266, 1967..
    [14] D. A. Buchanan, “Scaling the gate dielectric: Materials, integration, and reliability”, IBM J. Res. Dev. 43, 245, 1999.
    [15] G. E. Moore, The Experts Look Ahead 38, 8, 1965.
    [16] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics: current status and materials properties considerations”, Journal of Applied Physics 89, 5243, 2001.
    [17] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, “1.5 nm direct-tunneling gate oxide Si MOSFET’s”, IEEE Transactions On Electron Devices 43, 1233, 1996.
    [18] C. H. Choi, K. H. Oh, J. S. Goo, Z. Yu, and R. W. Dutton, “Direct tunneling current model for circuit simulation”, IEDM Technical Digest, 735, 1999.
    [19] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics: current status and materials properties considerations”, Journal of Applied Physics 89, 5243, 2001.
    [20] F. C. Chiu, S. K. Fan, K. C. Tai, and J. Y. Lee,” Electrical characterization of tunnel insulator in metal insulator tunnel transistors fabricated by atomic force microscope”, Applied Physics Letters 87, 243506-1, 2005.
    [21] S. Pan, S. J. Ding, Y. Huang, Y. J. Huang, D. W. Zhang, L. K. Wang, and R. Liu, “High-temperature conduction behaviors of HfO2 /TaN-based metal-insulator-metal capacitors”, Journal of Applied Physics 102, 073706-1 , 2007.
    [22] C. H. Liu, H. W. Chen, S. Y. Chen, H. S. Huang, and L. W. Cheng, ”Current conduction of 0.72 nm equivalent-oxide-thickness LaO/HfO2 stacked gate dielectrics”, Applied Physics Letters 95, 012103, 2009.
    [23] Y. Li, J. Zhu, H.Liu, and Z. Liu, “Fabrication and characterization of Zr-rich Zr-aluminate films for high-k gate dielectric applications”, Microelectronic Engineering 83, 1908, 2006.
    [24] P. W. Peacock and J. Robertson, “Behavior of hydrogen in high dielectric constant oxide gate insulators”, Applied Physics Letters 83, 2025, 2003.
    [25] J. Robertson, “Electronic structure and band offsets of high-dielectric-constant gate oxides”, Materials Research Society 27, 217, 2002.
    [26] W. J. Qi, R. Nieh, B. H. Lee, L. Kang, Y. Jeon, and J. C. Lee, “Electrical and reliability characteristics of ZrO2 deposited directlyon Si for gate dielectric application”, Applied Surface Science 77, 3269, 2000.
    [27] R. Mahapatra, G. S. Kar, C. B. Samantaray, A. Dhar, D. Bhattacharya, and S. K. Ray, “ZrO2 as a high-k dielectric for strained SiGe MOS devices”, Bulletin of Materials Science 25, 455, 2002.
    [28] J. McPherson, J. Kim, A. Shanware, H. Mogul, and J. Rodriguez, “Proposed universal relationship between dielectric breakdown and dielectric constant”, IEDM Tech. Digest, Digest, 633, 2002.
    [29] P. M. Abdala, M. C. A. Fantini, A. F. Craievich, and D. G. Lamas,” Crystallite size-dependent phases in nanocrystalline ZrO2-Sc2O3”, Phys. Chem, Chem. Phys. 12, 2822, 2010.
    [30] N. L. Zhang, Z. T. Song, Q. Wan, Wan, Q. W. Shen, and C. L. Lin “ Interfacial and microstructural properties of zirconium oxide thin films prepared directly on silicon”, Appl. Sur. Sci. 202, 126, 2002.
    [31] M. Gutowski, J. E. Jaffe, C. L. Liu, M. Stoker, R. I. Hegde, R. S. Rai, and P. J Tobin, “Thermodynamic stability of high-k dielectric metal oxides ZrO2 and HfO2 in contact with Si and SiO2”, Appl. Phys. Lett. 80,1897, 2002.
    [32] H. S. Choi, K. S. Seol, D. Y. Kim, and J. S. Kwak, “Thermal treatment effects on interfacial layer formation between ZrO2 thin films and Si substrates”, Vacuum 80, 310, 2005.
    [33] Y. H. Wu, L.L. Chen, W. C. Chen, C. C. Lin, M. L. Wu, Jia-Rong Wu, “ MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate”, Microelectronic Engineering, 88, pp.1361-pp1364, 2011.
    [34] G. He, Q. Fang, M. Liu, L. Q. Zhu, and L. D. Zhang, “The structural and interfacial properties of HfO2/Si by the plasma oxidation of sputtered metallic Hf thin films”, J. Cryst. Groth 268, 155, 2004.
    [35] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, “Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric”, IEEE Electron Device Letters 21, 181, 2000.
    [36] W. Zhu, T. P. Ma, T. Tamagawa, Y.Di, J. Kim, R. Carmthers, M. Gibson, and T. Furukawa, “HfO2 and HfAlO for CMOS: thermal stability and current transport”, IEDM Technical Digest, 463, 2001.
    [37] 白目靖寬、吉田貞史,”薄膜工程學”,全華科技圖書股份有限公司,2006。

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