近年來，因科技的快速發展，及人民生活水準提升。可攜式電子設備在其強調便利且功能完善下，深受社會大眾的廣大的需求。拜現今製成的進步，目前可攜式電子產品發展特色逐漸朝向輕薄短小，晶片系統積體電路的研發成果也功不可沒，其目的於縮小晶片面積、節省功率消耗、降低晶片製作成本、並有效提升整體系統效率等，而在消費者對產品的需求下，屬三角積分調變器的高解析度及對非理想效應性的不敏感等特點，已在儀器、音頻與通信上應用的相當廣泛。

本篇論文中，提出一個四倍取樣的三角積分調變器。在此架構中，使用四條路徑的取樣電路分別對訊號取樣，藉以提升整體系統的取樣頻率。且在積分時脈當中以創新重疊積分時脈想法來實現此電路。三角積分調變器不僅可以大幅提升類比數位信號的解析度，還達到降低功率消耗的目的。在TSMC 0.18 m 1P6M標準CMOS製程下，供應電壓為1.8 V，系統頻寬為20 kHz，等效的取樣頻率為10 MHz，所得到的訊號雜訊比為71.37 dB，總消耗功率為2.61 mW，整體面積大小為1.45*2.46 mm2。

In recent years, due to the rapid development of science and technology, and people's living standards. Portable electronic equipment in its emphasis on convenience and functional improvement, by the community's vast needs. Thanks to the progress of today's development, the current characteristics of portable electronic products gradually toward the light and thin, chip system integrated circuit research and development results also contributed to its purpose to reduce the chip area, saving power consumption, reduce wafer production costs, and Effectively enhance the overall system efficiency, and in the consumer demand for products, is a triangular integral modulator high resolution and non-ideal effect of insensitive and other characteristics, has been in the instrument, audio and communication applications rather widely.

In this paper, we propose a Quadruple Sampling Delta-Sigma Modulator. In this architecture, the four-path is used to sample the signal, thereby increasing the sampling frequency of the overall system. And make the integration clock overlapping overlapped with each other. Delta-Sigma Modulator can not only greatly enhance the analog digital signal resolution, but also to reduce the power consumption of the purpose. In the TSMC 0.18 m 1P6M standard CMOS process, the supply voltage is 1.8 V, the system bandwidth of 20 kHz, the equivalent sampling frequency of 10 MHz, the resulting signal to noise ratio of 71.37 dB, the total power consumption of 2.61 mW , The overall area size is 1.45 * 2.46 mm2.

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