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研究生: 鄧榮皓
Deng Rong Hao
論文名稱: 具有深度 STI 的NMOSFET 之應變工程模擬
Simulation of a sunken STI induced strained-NMOSFET
指導教授: 劉傳璽
Liu, Chuan-Hsi
學位類別: 碩士
Master
系所名稱: 機電工程學系
Department of Mechatronic Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 中文
論文頁數: 71
中文關鍵詞: 接觸蝕刻終止層淺溝槽隔離有限元素模擬載子遷移率
英文關鍵詞: CESL, STI, Finite element analysis, carrier mobility
論文種類: 學術論文
相關次數: 點閱:157下載:3
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  • 金氧半場效電晶體(MOSFET)節點技術不斷縮小至22奈米以下,因此在半導體應變工程中,接觸蝕刻終止層(CESL)與淺溝槽隔離(STI)被視為重要技術,兩種應力源可提高有效地電晶體的載子遷移率。而利用有限元素模擬的方法下,本研究探討在n型MOSFET中,STI幾何結構對於電晶體性能的影響。在上述條件下主要是利用不同製程方法讓矽通道的產生通道應力轉換以及CESL的內應力的影響進行分析。由模擬結果得知,具有深度的STI結構較無深度的STI更有用處,因為應力源所造成的Si通道的應力分佈是較高的。此外,藉由壓阻效應,可提高電晶體的載子遷移率的性能提高,由於上述的壓阻效應,可做出結論整合STI和CESL應力源可以有效的提高中10%〜20%載子遷移率。最後,對於電晶體應力分佈影響最重要的四個因子,閘極寬度、源∕汲極的長度、STI的長度、STI的深度。經過變異數分析結果後,源∕汲極長度與STI的深度這兩個因子對於載子遷移率增益的影響程度最為顯著。

    The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22 nm and beyond. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility. The critical geometric factors of the NMOSFET structure significantly affect the stress distribution in the channel region. Therefore, four critical designed factors including S/D lengths, gate width, STI length and depth of STI are analyzed to ANOVA. However, the effect of the S/D length on the device performance enhancement of NMOSFETs with a sunken STI stressor combined with a tensile CESL can be accurately calculated using 3D stress simulations.

    第一章 緒論 1 1.1 金氧半場效電晶體 1 1.2應變矽之工程技術 1 1.3有限元素法與實驗設計分析 1 1.4 本論文研究方向 2 第二章 文獻回顧 3 2.1奈米金氧半場效電晶體 3 2.1.1金氧半場效電晶體之類別與結構 4 2.1.2電晶體基本操作特性 5 2.1.3轉移特性ID-VG 6 2.2應變矽工程技術 8 2.2.1應力與應變關係 9 2.2.2彈性模數與浦松比 10 2.2.3等向性材料 10 2.2.4應變矽的物理機制 11 2.3 電晶體結構與多重應力源 12 2.3.1矽鍺通道之應變 13 2.3.2源/汲極填入矽鍺或矽碳合金 14 2.3.3接觸孔蝕刻終止層之影響 17 2.3.4淺溝槽隔離結構之影響 23 2.3.5具矽鍺合金通道與CESL應力的結構 27 2.3.3源/汲極填入矽鍺合金或矽碳化合物與CESL應力結構 29 2.4 壓阻效應 33 第三章 實驗設計 34 3.1 有限元素分析 34 3.1.1有限元素模型建立與求解 34 3.1.2模型的簡化 35 3.1.3模擬材料之性質與元素特性 37 3.1.4材料之參數與邊界條件 39 3.2具有深度的STI結構 39 3.2.1模擬步驟流程 39 3.3因子設計與變數分析 40 3.2.3反應曲面法 41 3.2.3最陡上升法 42 3.2.3中央合成設計 43 3.2.3 Box-Behnken 設計 44 3.2.3其他反應曲面設計 45 3.2.3模擬驗證與參數條件 46 第四章 結果與討論 48 4.1具深度STI與無深度之元件的影響 48 4.1.1探討STI應力對有具深度STI與無深度之元件的影響 51 4.1.2探討CESL拉應力對STI深度與無深度之模擬元件的影響 54 4.1.3探討CESL拉應力與STI應力對STI深度之模擬元件的影響 55 4.1.4探討CESL拉應力與STI應力對STI深度與無深度之載子遷移率的影響 57 4.2變異數分析 58 4.3反應曲面法 62 第五章 結論與未來展望 66 5.1探討具有無深度STI結構對半導體元件的影響 66 5.1因子設計與分析 67 5.2 未來展望 67

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