研究生: |
葉幸彰 Hsing-Chang Yeh |
---|---|
論文名稱: |
AES之超大型積體電路設計 VLSI Design of Advanced Encryption Standard |
指導教授: |
黃奇武
Huang, Chi-Wu 張吉正 Chang, Chi-Jeng |
學位類別: |
碩士 Master |
系所名稱: |
電機工程學系 Department of Electrical Engineering |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 中文 |
論文頁數: | 74 |
中文關鍵詞: | 高等加密標準 、現場可程式邏輯閘陣列 、特殊用途積體電路 、標準元件設計流程 |
英文關鍵詞: | AES, FPGA, ASIC, Cell-Based Design flow |
論文種類: | 學術論文 |
相關次數: | 點閱:190 下載:0 |
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高等加密標準(Advanced Encryption Standard, AES)硬體實現在現場可程式邏輯閘陣列(FPGA)與特殊用途積體電路(ASIC)已經被很廣泛的討論,尤其是如何達到數十億吞吐量的議題;然而本實驗室近幾年在FPGA設計成果很多,但尚未實現標準元件設計,因此本研究將實驗室團隊開發的AES硬體架構改善,並架設工作站透過數位電路設計流程實現AES加密晶片。
首先本研究利用國家晶片研究中心提供的工具,將數位電路設計所需的環境與軟硬體架設起來,建立一套完整的數位晶片設計平台。接著本研究提出8位元輸入輸出的AES硬體電路架構,並搭配BRAM(包含RAM和ROM),或使用組合邏輯運算去設計,分析其在電路設計上實現在FPGA與透過標準元件設計流程實現在ASIC上,從數據得知,其未使用BRAM的8位元輸入輸出的AES gate count為2.2k,是在目前搜尋文獻中面積最小的設計。
Advance Encryption Standard (AES) hardware implementation in FPGA and ASIC have been intensely discussed, especially in high-throughput of Giga bit per second (Gbps). However, our team have many designs in FPGA in the recent years but not yet implemented in Cell-Based Design. Therefore, this paper improve the hardware architecture of AES , setup the environment and server , Then through Cell-Based Design flow to implement the AES Chip.
First, this paper use the EDA tools provided by the National Chip Implementation Center to setup the environment for a complete platform of digital chip design. Then, This paper presents an 8-bit AES implementation with BRAM (using RAM or ROM) or without BRAM(using combinational circuits) in order to achieve design. Finally, we compare the data of FPGA and ASIC. By the results of ASIC, the area of AES without BRAM is 2.2k gate count, which is the smallest design among literature reports.
[1] NIST. Announcing the advanced encryption standard (AES), FIPS 197. Technical report, National Institute of Standards and Technology, November 2001.
[2] Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh, “A Compact Rijndael Hardware Architecture with S-Box Optimization,” Advances in Cryptology — ASIACRYPT 2001 7th International Conference on the Theory and Application of Cryptology and Information Security Gold Coast, Australia, December 9–13, 2001 Proceedings, January 2001.
[3] J. Wolkerstorfer, E. Oswald, M, Lamberger, “An ASIC Implementation of the AES SBoxes,” CT-RSA 2002, LNCS 2271, pp-67-78, 2002.
[4] M. Feldhofer, S. Dominikus, and J. Wolkerstorfer, ”Strong authentication for RFID systems using the AES algorithm,” In Proc. 6th Int. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2004), Boston, MA, USA, Aug. 11–13, 2004, pages 357–370.
[5] Panu Hämäläinen, Timo Alho, Marko Hännikäinen, and Timo D. Hämäläinen, “Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core,” Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on, 2006,pp- 577 - 583
[6] Chi-Jeng Chang, Chi-Wu Huang, Hung-Yun Tai, Mao-Yuan Lin and Teng-Kuei Hu, “8-bit AES FPGA Implementation using Block RAM,” The 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON), Nov. 5-8, 2007, Taipei, Taiwan, pp.2654-2659
[7] Chi-Jeng Chang, Chi-Wu Huang, Hung-Yun Tai, Mao-Yuan Lin, "8-bit AES Implementation in FPGA by Multiplexing 32-bit AES Operation," The First International Symposium on Data,Privacy, and E-Commerce (ISDPE 2007),pp. 505-507.
[8] Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, Hung-Yun Tai, “Compact FPGA Implementation of 32-bits AES Algorithm Using Block RAM,” The IEEE international technical conference sponsored(TENCON) from 30 Oct to 2 Nov 2007.in Taipei, Taiwan, FrCN-O12.1,598.
[9] Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, Hung-Yun Tai, "The FPGA Implementation of 128-bits AES AlgorithmBased on Four 32-bits Parallel Operation," The First International Symposium on Data, Privacy, and E-Commerce (ISDPE 2007) isdpe, pp. 462-464,
[10] Chi-Jeng Chang, Chi-Wu Huang, Kuo-Huang Chang, Yi-Cheng Chen and Chung-Cheng Hsieh,"High Throughput 32-bit AES Implementation in FPGA,"IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, December 2008, MACAO, pp. 1806 – 1809.
[11] Kuo-Huang Chang, Yi-Cheng Chen, Chung-Cheng Hsieh, Chi-Wu Huang and Chi-Jeng Chang,"Embedded a Low Area 32-bit AES for Image Encryption/Decryption Application,"IEEE International Symposium on Circuits and Systems,May 2009, Taipei, Taiwan, pp. 1922 - 1925.
[12] Chi-Wu Huang,Ying-Hao TU,Shih-Hao Liu,Hsing-Chang Yeh, "The Platform Built Based on the Mode operations of AES and the Image Applications" , International Journal of Modern Education and Computer Science (IJMECS), China ,April 2011, PP.1-8
[13] Chi-Wu Huang, Shih-Hao Liu, Ying-Hao Tu, Chi-Jeng Chang, "Understanding AES and the Operation Modes in Image Encryption," etcs, 2011 Third International Workshop on Education Technology and Computer Science, pp.51-54, May 2011.
[14] Chi-Wu Huang, Ying-Hao Tu, Hsing-Chang Yeh, Shih-Hao Liu, Chi-Jeng Chang, "Image observation on the modified ECB operations in Advanced Encryption Standard,"Information Society (i-Society), 2011 International Conference on, June 2011, London, UK, pp. 264 – 269.
[15] Chi-Wu Huang, Hong-You Chen, Hsing-Chang Yeh, Chi-Jeng Chang , "Block RAM Based Design of 8-bit AES Operation Modes," , IWIEE, China Harbin,January 2012, pp. 2848-2852 .
[16] G. Rouvroy, F.-X. Standaert, J.-J. Quisquater, J.-D. Legat, "Compact and efficient encryption/decryption module for FPGA implementation of the AES very well suited for small embedded applications", Information Technology Coding and Computing, 2004. Proceedings. ITCC 2004, Volume 2, Page(s):583 - 587 Vol.2, 2004.
[17] Tim Good, Mohammed Benaissa, "Very small FPGA application-specific instruction processor for AES", IEEE Trans. Circuit and System,vol. 53, no. 7, 2006
[18] Tim Good, Mohammed Benaissa, “692-nW Advanced Encryption Standard (AES) on a 0.13- um CMOS,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 12, DECEMBER 2010.
[19] X. Zhang and K. K.Parhi “High Speed VLSI Architectures for the AES Algorithm,” IEEE Trans. VLSI Systems, vol. 12, no. 9, September 2004.
[20] M. Feldhofer, J. Wolkerstorfer, and V. Rijmen, “AES implementation on a grain of sand,” Proc. Inst. Electr. Eng. Inf. Security, vol. 1, pp.13–20, 2005.
[21] Pawel Chodowiec and Kris Gaj, “Very Compact FPGA Implementation of the AES Algorithm”, Cryptographic Hardware and Embedded Systems, vol. 2779, pp. 319–333, September 2003.
[22] Jyh-Huei Guo and Chin-Liang Wang,” Systolic Array Implementation of Euclids Algorithm for Inversion and Division in GF (2m),” IEEE Trans. Computers, vol. 47, no. 10, October 1998.
[23] Hannes Brunner, Andreas Curiger, and Max Hofstetter, “”On Computing Multiplicative Inverses in GF (2m),” IEEE Trans. Computers, vol. 42, no. 8, August 1993.
[24] William Stallings, Cryptography and Network Security: Principles and Practice. Prentice Hall, 1999.
[25] CIC 訓練課程– VHDL.
[26] CIC 訓練課程– Verilog.
[27] 王旭昇,”Logic Synthesis with Design Compiler,” CIC 訓練課程2008。
[28] 詹慶達,”Cell-Based IC Physical Design and Verification with IC Compiler,” CIC 訓練課程2011。
[29] 黃俊銘,”Cell-Based IC Design Concepts,” CIC 訓練課程2008。
[30] CIC設計服務組,” CIC Referenced Flow for Cell-based IC Design,” 2007。