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研究生: 葉幸彰
Hsing-Chang Yeh
論文名稱: AES之超大型積體電路設計
VLSI Design of Advanced Encryption Standard
指導教授: 黃奇武
Huang, Chi-Wu
張吉正
Chang, Chi-Jeng
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 74
中文關鍵詞: 高等加密標準現場可程式邏輯閘陣列特殊用途積體電路標準元件設計流程
英文關鍵詞: AES, FPGA, ASIC, Cell-Based Design flow
論文種類: 學術論文
相關次數: 點閱:190下載:0
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  • 高等加密標準(Advanced Encryption Standard, AES)硬體實現在現場可程式邏輯閘陣列(FPGA)與特殊用途積體電路(ASIC)已經被很廣泛的討論,尤其是如何達到數十億吞吐量的議題;然而本實驗室近幾年在FPGA設計成果很多,但尚未實現標準元件設計,因此本研究將實驗室團隊開發的AES硬體架構改善,並架設工作站透過數位電路設計流程實現AES加密晶片。
      首先本研究利用國家晶片研究中心提供的工具,將數位電路設計所需的環境與軟硬體架設起來,建立一套完整的數位晶片設計平台。接著本研究提出8位元輸入輸出的AES硬體電路架構,並搭配BRAM(包含RAM和ROM),或使用組合邏輯運算去設計,分析其在電路設計上實現在FPGA與透過標準元件設計流程實現在ASIC上,從數據得知,其未使用BRAM的8位元輸入輸出的AES gate count為2.2k,是在目前搜尋文獻中面積最小的設計。

    Advance Encryption Standard (AES) hardware implementation in FPGA and ASIC have been intensely discussed, especially in high-throughput of Giga bit per second (Gbps). However, our team have many designs in FPGA in the recent years but not yet implemented in Cell-Based Design. Therefore, this paper improve the hardware architecture of AES , setup the environment and server , Then through Cell-Based Design flow to implement the AES Chip.
    First, this paper use the EDA tools provided by the National Chip Implementation Center to setup the environment for a complete platform of digital chip design. Then, This paper presents an 8-bit AES implementation with BRAM (using RAM or ROM) or without BRAM(using combinational circuits) in order to achieve design. Finally, we compare the data of FPGA and ASIC. By the results of ASIC, the area of AES without BRAM is 2.2k gate count, which is the smallest design among literature reports.

    摘  要 i ABSTRACT ii 誌  謝 iii 目  錄 iv 圖 目 錄 vi 表 目 錄 viii 第一章  緒論 1 1.1  研究背景 1 1.2  研究動機 3 1.3  研究目的 4 1.4  研究步驟 5 第二章  AES與ASIC介紹 6 2.1  AES(Advanced Encryption Standard)介紹 6 2.1.1 AES演算法 6 2.1.2 數學背景 8 2.1.3 位元組替換與反位元組替換(SubByte / InvSubByte) 9 2.1.4 移列運算與反移列運算(ShiftRow / InvShiftRow) 12 2.1.5 混行運算與反混行運算(MixColumn / InvMixColumn) 13 2.1.6 回合金鑰加法運算(AddRoundkey) 14 2.1.7 金鑰擴展(KeyExpansion) 15 2.2  ASIC(Application-Specific Integrated Circuit) 18 2.2.1 何謂數位積體電路設計 18 2.2.2 基本邏輯閘(Gate) 19 2.2.3 電子設計自動化(Electronic Design Automation) 21 2.2.4 IC設計流程 21 第三章  文獻探討 28 3.1  Xinmiao Zang架構 28 3.2  Johannes Wolkerstorfer架構 31 3.3  Geal Rouvroy架構 34 3.4  Akashi Satoh架構 36 3.5  Pawel Chodowiec架構 39 第四章  AES硬體電路設計 41 4.1  8位元AES硬體電路架構 41 4.2  8位元AES之FPGA模擬驗證 43 4.3  8位元AES之FPGA效能比較 50 第五章  Cell-Based Design模擬分析與實現 51 5.1  工作站平台規劃 51 5.2  設計流程 53 5.3  8位元AES 之ASIC設計 54 5.3.1 RTL層模擬(RTL-level Simulation) 54 5.3.2 邏輯合成(Logic Synthesis) 56 5.3.3 自動佈局與繞線(Auto Place & Route) 57 5.3.4 位元AES 之ASIC實現 64 5.4  FPGA與ASIC分析比較 67 第六章  結論與未來展望 68 參考文獻 69

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