簡易檢索 / 詳目顯示

研究生: 施登耀
Deng-Yao Shi
論文名稱: 應用於音頻之低功率高效能三角積分調變器設計與實現
The Design and Implementation of Low-power High-performance Delta-Sigma Modulators for Audio Application
指導教授: 郭建宏
Kuo, Chien-Hung
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 101
中文關鍵詞: 類比數位轉換器三角積分調變器強健式多級雜訊頻移架構數位前饋架構逐次逼近暫存式類比數位轉換器
英文關鍵詞: Analog-to-digital converter, delta-sigma modulator, Sturdy Multi-stage Noise Shaping, Digital feed-forward, successive approximation register ADC
論文種類: 學術論文
相關次數: 點閱:168下載:39
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在現今製程技術不斷的進步下,積體電路設計已進入了奈米時代,此進步不但大大的降低了電路的面積,相對上電源供應電壓也大幅的下降。高效能、低功率的晶片陸續地推陳出新,以及人們對於產品輕薄短小和電池的長時效性要求,低功率積體電路技術發展有愈來愈急迫的需要。然而,電源電壓的下降,雖可有效地節省數位電路的消耗功率,但卻反而增加類比數位轉換電路設計的困難。在許多應用當中,類比數位轉換器(Analog-to-digital converter)佔著舉足輕重的角色,而有許多種架構可以來完成。三角積分調變器(Delta Sigma Modulator)對類比電路的非理想特性並不敏感,這些特性包含元件之間的不匹配、運算放大器的增益等等。然而這些特性恰巧對低功率電路來說尤其重要。三角積分調變器這項技術基本上非常適合用來實現高解析度、高準確度、及窄頻要求的類比數位轉換器,因此在儀器、音頻及通信上的應用已相當的普遍。

    在本論文中,提出了兩種新穎的架構並且實現,一是改良強健式多級雜訊頻移架構(Sturdy Multi-stage Noise Shaping, SMASH),降低運算放大器對電壓增益的需求,並結合數位前饋架構(Digital feed-forward),增加輸入動態範圍且降低失真;二為,三角積分調變器使用逐次逼近暫存式(Successive Approximation Register, SAR)類比數位轉換器,此架構可有效降低功率消耗和電路複雜度。兩架構實現所使用的製程技術分別為TSMC 90-nm 1P9M CMOS與TSMC 0.18-mm 1P6M CMOS;設計的供應電壓皆為1.2 V、頻寬為音頻應用的25 kHz;模擬結果分別達到的最大SNDR為63 dB與82 dB;電源功率消耗分別為813 mW與463 mW。

    The fabrication of integrated circuit has entered the nano-grade with the improvement of modern technology. This progress not only reduces the circuit area greatly, but also lowers the supply voltage significantly. Chips with high-performance and low-power have been proposed constantly today, the main demand of these chips nowadays is more power saving for portability. Hence, the low power technology has become a trend in modern integrated circuit designs. Although the decreasing of the supply voltage can effectively save power consumption of digital circuits, it also increases the difficulty of designing analog-to-digital converters (ADCs) circuits, which plays an important role in many applications. Fortunately, Delta-sigma modulators are insensitive to the imperfections of the analog components, including the mismatch between elements, the gain of OPAMPs, etc… which are of great influence to low-power chips. Therefore, they’re usually designed and applied for high-resolution systems such as instruments, audio devices, and communication devices.

    In this thesis, we propose and construct two new structures. The first one is an improved Sturdy Multi-stage Noise Shaping (SMASH) structure. Here are three key-points of SMASH: (a) it reduces the gain requirement of the operational amplifier (OPAMP) (b) analogy modulator adopting the Digital feed-forward (DFF) path (c)input dynamic range larger than conventional DSM with the distortion of modulator reduced. The second structure is a  modulator using successive approximation register (SAR) ADC. This architecture reduces power consumption and simplifies circuit complexity. Two of the modulators are constructed in 90-nm 1P9M CMOS and 0.18-m 1P6M CMOS process technology, respectively. Both modulators process 25-KHz audio-band, with 63 dB and 82dB peak SNDR. Total power dissipations are 813 mW and 463 mW, respectively.

    摘  要 I ABSTRACT II 誌  謝 IV 目  錄 V 圖 目 錄 VIII 表 目 錄 XI 第一章  緒論 1 1.1 研究動機與背景 1 1.2 論文組成 2 第二章 概論 3 2.1 前言 3 2.2效能標準 4 2.2.1訊號雜訊比 4 2.2.2訊號雜訊失真比 4 2.2.3無雜波干擾之動態範圍 5 2.2.4動態範圍 5 2.2.5解析度 6 2.3量化器 6 2.3.1單位元量化器 7 2.3.2多位元量化器 8 2.3.3量化誤差 10 2.4超取樣技術 12 2.5雜訊移頻的三角積分調變器 14 2.5.1一階雜訊移頻 16 2.5.2二階雜訊移頻 19 2.5.3高階雜訊移頻 21 第三章 電路元件設計 27 3.1交換電容式電路 27 3.1.1離散時間反向積分器 27 3.1.2離散時間非反向積分器 28 3.2開關電路 29 3.2.1 NMOS開關與PMOS開關 29 3.2.2傳輸閘開關 29 3.2.3低臨界電壓製程技術 31 3.2.4倍壓開關電路 31 3.2.5靴帶式開關 32 3.3運算放大器 34 3.4偏壓電路 36 3.5共模回授電路 37 3.6多位元量化器 37 3.7比較器電路 38 3.8動態原件匹配 39 3.8.1資料權重平均 39 3.8.2時脈平均演算法 40 第四章 延遲數位前饋強健式多級三角積分調變器 43 4.1 三角積分調變器架構考量 43 4.1.1 強健式多級三角積分調變器 43 4.1.2數位前饋三角積分調變器 45 4.1.3延遲數位前饋強健式多級三角積分調變器 46 4.2 線性模型的MATLAB模擬 48 4.2.1架構的比較 48 4.2.2電路的非理想效應 51 4.3 架構的電路設計與實現 58 4.3.1積分增益與最小電流 59 4.3.2運算放大器設計 63 4.3.3架構電路模擬結果 66 4.3.4電路佈局實現 68 4.4晶片量測 71 4.4.1輸入訊號與輸入終端電路 71 4.4.2供應電壓電路 72 4.4.3濾波槽 73 4.4.4量測結果 74 4.5結論 76 第五章 三角積分調變器使用逐次逼近暫存式類比數位轉換器 77 5.1三角積分調變器架構考量 77 5.2 線性模型的MATLAB模擬 80 5.2.1系統架構的模擬與分析 80 5.2.2系統架構的非理想模擬 83 5.3 架構的電路設計與實現 85 5.3.1積分增益與最小電流 86 5.3.2運算放大器設計 86 5.3.3架構電路模擬結果 87 5.3.4電路佈局實現 88 5.4晶片量測 90 5.4.1量測結果 91 5.5結論 93 第六章 總結與未來展望 95 6.1 總結 95 6.2 未來展望 96 參 考 文 獻 98

    [1] R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Second Edition, Wiley, IEEE Press, 2008.
    [2] D. A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
    [3] J. Silva, U. K. Moon, J. Steensgaard, and G. C. Temes, “Wideband Low-Distortion Delta-Sigma ADC Topology,” Electron. Lett., vol. 37, pp. 737-738, Jun. 2001
    [4] S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1996
    [5] R. Schreier and G. C. Temes, Understanding Delta–Sigma Data Con verters: New York: Wiley, 2004.
    [6] K. C. H. Chao, S. Nadeem, W. L. Lee, and C. G. Sodini, “A Higher-Order Topology for Interpolative Modulators for Oversampling A/D Converters,” IEEE Trans. Circuits Syst., vol. 37, no. 3, pp. 309-318, Mar. 1990.
    [7] W. L. Lee and C. G. Sodini, “A Topology for Higher-Order Interpolative Coders,” in Proc. IEEE Intel. Symp. Circuits Syst., 1987, pp.459-462.
    [8] B. DelSignore, D. Kerth, N. Sooch, anf E. Swansooon, “ A Monolithic 20-B Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1311-1317, Dec. 1990.
    [9] T. Ritoniemi, T. Karema, and H. Tenhunen, “The Design of Stable High Order 1-Bit Sigma-Delta Modulators,” in Proc. IEEE Intel. Symp. Circuits Syst., May 1990, pp. 3267-3270.
    [10] P. Ferguson, A. Ganesan, R. Adarns, S. Vincelette, R. Libert, A. Volpe, D. Andreas, A.Charpentier, and J. Dattorro, “An 18b 20KHz Dual SD A/D Converter,” in Proc. ISSCC, Feb. 1991, pp. 68-292.
    [11] T. Tille, J. Sauerbrey, and D. Schmitt-Landsiedel,” A Low-Voltage MOSFET-Only SD Modulator for Speech Band Applications Using Depletion-Mode MOS-Capacitors in Combined Series and Parallel Compensation,” in Proc. IEEE Intel. Symp. Circuits Syst., May 2001, pp. 376-379.
    [12] J. Sauerbrey, T. Tille, D. S. Landsiedel, and R. Thewes, “A 0.7-V MOSFET-Only Switched-Opamp SD Modulator in Standard Digital CMOS Technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1662-1669 Dec. 2002
    [13] P. Favrat, P. Deval, and M. J. Declercq, “An improved voltage doubler in a standard CMOS technology,” in Proc. IEEE Intel. Symp. Circuits Syst., Hong Kong, June 1997, pp. 249-252
    [14] P. Favrat, P. Deval, and M. J. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, Mar. 1998.
    [15] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched op amp circuits,” Electron. Lett., vol. 35, no. 1, pp. 8-10, Jan. 1999
    [16] G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Hamashita, K. Takasuka, G.Temes, and U. K. Moon, “0.6-V 82-dB Delta-Sigma Audio ADC using Switched-RCIntegrators,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2398-2461, Dec. 2005.
    [17] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol.39, no.11, pp.1809-1818, Nov. 2004
    [18] R. Jacob Baker, CMOS: Circuit Design, Layout, and Simulation, Revised Second Edition, Wiley, IEEE Press, 2008.
    [19] A. Lopez-Martin, S. Baswa, J. Ramírez-Angulo, and R. G. Carvajal, “Low-voltage super Class-AB CMOS OTA cells with very high slew rate and power efficiency,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1068-1077, May 2005.
    [20] C.-H. Kuo, D.-Y. Shi, and K.-S. Chang, “Low-Voltage Fourth-Order Cascade Delta–Sigma Modulator in 0.18-μm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2450-2461, Sep. 2010.
    [21] P. M. Figueiredo, and J. C. Vital, “Kickback Noise Reduction Techniques for CMOS Latched Comparators” , IEEE Trans. Circuits Syst. II, Express Briefs, vol. 53, no. 7, pp. 541-545, July 2006.
    [22] Da-Huei Lee and Tai-Haur Kuo, “Advancing Data Weighted Averaging Technique for Multi-Bit Sigma-Delta Modulators” , IEEE Trans. Circuits Syst. II, Express Briefs, vol. 54, no. 10, pp. 838-842, Oct. 2007.
    [23] N. Maghari, S. Kwon, G.C. Temes and U. Moon, “Sturdy MASH D-S modulator,” Electron. Lett., vol. 42, no. 22, pp. 1269-1270, Oct. 26, 2006.
    [24] N. Maghari, S. Kwon and U. Moon, “74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2212-2221, Aug. 2009.
    [25] N. Maghari, S. Kwon, G. C. Temes, and U. Moon, “Mixed-Order Sturdy MASH D-S Modulator,” in Proc. IEEE Intel. Symp. Circuits Syst., New Orleans, LA, May 2007, pp. 257-260.
    [26] A. A. Hamoui, M. Sukhon, and F. Maloberti, “Digitally-Enhanced 2nd-Order SD Modulator with Unity-Gain Signal Transfer Function,” in Proc. IEEE Intel. Symp. Circuits Syst., Seattle, WA, May 2008, pp.1664-1667.
    [27] A. A. Hamoui, M. Sukhon, and F. Maloberti, “Digitally-Enhanced High-Order DS Modulators,” in Proc. IEEE Intel. Conf. Electron. Circuits Syst., St. Julien's, Aug. 31 2008-Sept. 3 2008, pp. 1115-1118.
    [28] A. Gharbiya, and D. A. Johns, “On the implementation of input feedforward delta-sigma modulators,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 53, no. 6, pp. 453-457, June 2006.
    [29] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc. New York, NY, USA, 2001.
    [30] H. Park, K.g Nam, D. K. Su, K. Vleugels, and B. A. Wooley, “A 0.7-V 870-uW Digital-Audio CMOS Sigma-Delta Modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1078-1088, Apr. 2009.
    [31] V. Peluso, P. Vancorenland, A. M. Marques, M. S. Steyaert, and W. Sansen, “A 900-mV low-power DS A/D converter with 77-dB dynamic range,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp.1887-1897, Dec. 1998.
    [32] J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes, “A 0.7V MOSFET-only switched opamp DS modulator in Standard Digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1662-1669, Dec. 2002.
    [33] J. Goes, B. Vaz, R. Monteiro, and N. Paulino, “A 0.9 V DS modulator with 80 dB SNDR and 83 dB DR using a single-phase technique,” in Proc. ISSCC, Feb. 2006, pp. 74-75.
    [34] S. Kwo and F. Maloberti, “A 14mW Multi-bit SD Modulator with 82dB SNR and 86dB DR for ADSL2+,” in Proc. ISSCC, Feb. 2006, pp. 161-170.
    [35] K.-P. Pun, S. Chatterjee, and P. R. Kinget, “A 0.5-V 74-dB SNDR 25-kHz continuous-time delta-sigma modulator with a return-to-open DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 496-507, Mar. 2007.
    [36] J. Roh, S. Byun, Y. Choi, H. Roh, Y.G. Kim, and J.K. Kwon, “A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361-370, Feb. 2008.
    [37] A. Gharbiya, and D. A. Johns, “A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2010-2018, July 2009.
    [38] Y. Chae, and G. Han, “Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 458-472 Feb. 2009.
    [39] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Ying-Zu Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure” , IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740 Apr. 2010.

    下載圖示
    QR CODE