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研究生： 林孟霆
Lin, Meng-Ting
論文名稱： 24-GHz低雜訊放大器之靜電放電防護設計
On-Chip ESD Protection Design for 24-GHz LNA
指導教授： 林群祐
Lin, Chun-Yu
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 85
中文關鍵詞： 靜電放電 、矽控整流器 、低雜訊放大器
英文關鍵詞： Electrostatic discharge, silicon-controlled rectifier, low-noise amplifier
DOI URL： https://doi.org/10.6345/NTNU202203079
論文種類： 學術論文
相關次數： 點閱：115  下載：13 
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    • 本論文主旨為應用於射頻積體電路之全晶片靜電防護電路，本論文設計了兩種應用於高頻積體電路的靜電放電防護設計，並與先前論文所提出的傳統防護電路來做比較。所下線之晶片皆使用0.18um CMOS製程。

    傳統靜電放電箝制電路已被廣泛應用於靜電放電防護設計之中，然而其高佈局面積在先進製程中往往會是個麻煩，因此本篇論文利用矽控整流器低佈局面積與優秀靜電防護能力特性，來加以改善傳統電路，而矽控整流器的閂鎖效應與導通速度過慢問題，本論文也提出了解決方法；本論文提出使用內嵌入式矽控整流器二極體串來改良原先P型與N型二極體的靜電放電能力，透過量測結果比較，本論文提出的兩種靜電放電防護設計皆能在單一面積下提供最佳的靜電耐受度並擁有且較低損耗值。

    為了驗證靜電防護電路應用於高頻電路的實際功用，本論文也設計了24GHz低雜訊放大器並搭配適當尺寸的防護電路，在量測結果中，本論文所提出的防護設計並不會影響高頻電路之響應。

    This essay is to design an effective whole-chip ESD protection circuits for RF integrated circuit. In this essay, two types of ESD protection designs, which apply to RF integrated circuits has been proposed and compared with conventional ESD protections. All of circuits in this essay are fabricated in 0.18-um CMOS process.

    The conventional power-rail ESD clamp circuit has been used widely in ESD protection designs. However, the high layout area of conventional circuit is an issue in advanced process. Therefore, using silicon-controlled rectifier (SCR) with low layout area and excellent ESD protection ability improves the issue of the conventional power-rail ESD clamp circuit that is high layout area. Furthermore, solutions of the latch-up problem and slow-trigger-on speed of SCR have been proposed. In this essay, using the diode string with embedded SCR improves the issue of p-type and n-type diodes. Through the comparison of measurement results, two types of ESD protection designs can provide the best ESD robustness and the lowest loss at unit area.

    In order to verify the practical function of ESD protection circuit on RF circuit, the low-noise amplifier (LNA) with the appropriate size of ESD protection circuit has been designed. In measurement results, proposed designs do not affect the RF performance.

    Contents Abstract (Chinese) I Abstract (English) II Acknowledgement III Contents V Table Captions VIII Figure Captions IX Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Background of ESD 2 1.3 Testing Methods 2 1.4 Background of Whole-Chip ESD Protection Circuit 4 1.5 Organization of This Dissertation 9 Chapter 2 Whole-Chip ESD Protection Circuit Design 10 2.1 ESD Protection Component 10 2.1.1 Diode 10 2.1.2 SCR 12 2.1.3 DSSCR 14 2.2 Design of Power-Rail ESD Clamp 16 2.3 Whole-Chip ESD Protection Circuit 18 2.3.1 Prior Arts 18 1. Dual Diodes with MOS-Based Power-Rail ESD Clamp (DD_MOS) 18 2. Dual Stacked Diodes with MOS-Based Power-Rail ESD Clamp (DSD_MOS) 19 2.3.2 Proposed Designs 22 1. Dual Stacked Diodes with SCR-Based Power-Rail ESD Clamp (DSD_SCR) 22 2. DSSCR with SCR-Based Power-Rail ESD Clamp (DSSCR_SCR) 22 2.4 Experimental Results 25 2.4.1 High-Frequency Performances 25 2.4.2 TLP I-V Curves 28 2.4.3 HBM Measurement Results 30 2.4.4 CDM Measurement Results 31 2.4.5 Leakage 32 2.4.6 Comparison 33 2.5 Summary 36 Chapter 3 24-GHz Low-Noise Amplifier 37 3.1 Introduction 37 3.2 Transistor Noise Sources 38 3.2.1 Thermal Noise 38 3.2.2 MOSFET Gate Resistance Noise 40 3.2.3 Flicker Noise 40 3.3 Parameters of Designing Low-Noise Amplifier 41 3.3.1 Gain 41 1. Transducer Power Gain 41 2. Available Power Gain 41 3. Operating Power Gain 42 3.3.2 Stability 42 3.3.3 Noise Figure 43 3.4 Circuit Design Steps 44 3.4.1 Design of Transistor Bias 44 3.4.2 Design of Transistor Size 46 3.4.3 Design of Source Degeneration Inductor 47 3.4.4 Design of Matching Network 48 1. Input-Stage Matching Network 49 2. Stage-to-Stage Matching Network 50 3. Output-Stage Matching Network 51 3.4.5 Design of Bias Circuit 52 3.5 LNA Simulation Results 53 3.5.1 LNA 53 3.5.2 LNA with ESD Protection Circuit 55 3.6 LNA Measurement Results 60 3.6.1 LNA 60 3.6.2 LNA with ESD Protection Circuit 63 1. TLP I-V Curves 64 2. High-Frequency Performance 66 3.7 Discussion and Summary 74 3.7.1 Debug 74 3.7.2 Summary 75 Chapter 4 Conclusion and Future Works 77 4.1 Conclusion 77 4.2 Future Works 78 Reference 80 Vita 84 Publication List 85

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