研究生: |
張欽德 Cin-De Jhang |
---|---|
論文名稱: |
應用於極座標發射機封包調變之六位元置中型數位脈波寬度調變器的設計與實現 Design and Implementation of a 6-Bit Center-Aligned Digital Pulse-Width Modulator for Envelope Modulation of Polar Transmitters |
指導教授: |
郭建宏
Kuo, Chien-Hung |
學位類別: |
碩士 Master |
系所名稱: |
電機工程學系 Department of Electrical Engineering |
論文出版年: | 2014 |
畢業學年度: | 102 |
語文別: | 中文 |
論文頁數: | 120 |
中文關鍵詞: | 數位脈波寬度調變器 、LTE極座標發射器 、封包調變器 |
英文關鍵詞: | Digital Pulse Width Modulator, LTE polar modulation transmitter, Envelope modulatior |
論文種類: | 學術論文 |
相關次數: | 點閱:171 下載:3 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在傳統的發射機應用中,常見的兩種封包調變器架構為三角積分調變器、與脈波寬度調變器。雖然DSM架構實現容易,但在LTE寬頻的要求下,多位元的輸出往往會增加後續PA在實現上的難度。PWM架構雖然有輸出諧波的困擾,但若能提高取樣操作頻率,及實現的脈波寬度線性度,其單位元的輸出將可大大降低PA實現的複雜度,解決諧波失真也只要在功率放大器後端增加帶通濾波器來濾除諧波失真。
為了提高脈波寬度調變器的信號線性度,我們將輸出的脈波置中對齊。相較於靠邊型PWM,置中型減少許多諧波失真,提高整體發射機效能。本論文以6位元置中型的PWM為例,其結果比靠邊型PWM有較佳的調變性能展現,而採用混合型的脈波寬度調變器架構,能減少不必要的延遲元件以及降低高速的計數器切換。
應用於LTE極座標發射器封包調變的脈波寬度調變器,設計全數位式置中混合型脈波寬度調變器。在所提出的調變器中,我們藉由延遲鎖定迴路所提供的128個相位,合成64種置中型脈波寬度的輸出,完成6 位元LTE信號的調變器要求。為了降低多重相位延遲鎖定迴路的延遲元件數目,我們使用一個簡單的計數器將相位輸出區分為上升及下降兩類。並將輸入脈波轉換成脈衝,以便環繞multi-phase VCDL來得到128個相位的輸出。最後經由多工器的選取,以及邊緣合成器合成64種寬度的置中型脈波。本論文採用TSMC 90 nm 1P9M量測輸入92.16 MHz在1.2 V的電源電壓下,量測的功率為22.05mW,而使用TSMC 90nm GUTM 模擬結果在122.88 MHz供應電壓為1 V以下,功率為30.82mW。
The pulse-width modulation (PWM) and delta-sigma modulation (DSM) are two popular approaches used for the realization of the envelope modulator in traditional polar transmitters. Although DSM provides an easy structure for implementation, multi-bit outputs due to the requirements of linearity and wide bandwidth in modern communications would make the design of post-PAs difficult to be realized. Fortunately, if the operational frequency of PWM could be appropriately increased, the annoying harmonic effect would be easily attenuated by the post-bandpass filter.
In this thesis, a hybrid digital PWM (DPWM) having counter and delay cells is devised to compromise between area cost and operational speed. To increase the linearity of DPWM, the center-aligned pulse technology is adopted in the presented modulator. Sixty-four different pulse widths of outputs corresponding to the 6-bit input signal are designed in the presented modulator. The center-aligned output pulses exhibits lower noise floor near the interest band than the edge-aligned counterpart.
This thesis presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is measured in TSMC 90nm 1P9M RF process. The power consumption is 22.05 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2 V, and the other simulated in TSMC 90nm 1P9M GUTM process. The power consumption is 36.82 mW at a 122.88 MHz input reference frequency and a supply voltage of 1 V.
[1] L. R. Kahn, “Single-Sideband Transmission by Envelope Elimination and Restoration,” Proc. IRE, vol. 40, no.7, pp. 803-806, Jul. 1952.
[2] L. R. Kahn, “Intermodulation distortion in Kahn-technique transmitters,” IEEE Trans.on Microwave Theory Tech, vol. 40, no.7, pp. 803-806, Jul. 1952.
[3] E. McCune, “Advanced architectures for high-efficiency multi-mode, multi-band terminal power amplifiers,” in Proc. IEEE Radio Wireless Conf., 2004, pp.167-170.
[4] P. T. M. van Zeijl, and M. Collados, “A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2204-2211, Oct. 2007.
[5] K. C. Peng, J. K. Jau and T. S. Horng, “A novel EER transmitter using two-point delta-sigma modulation scheme for WLAN and 3G applications,” in Proc. IEEE MTT-S Int. Microwave Symp. Dig., 2002, pp. 1651-1654.
[6] I . Zhang, B. Shi, and Y. Lian, “Performance Evaluation on Polar Transmitters Using Delta and Sigma modulations,” in Inter. Conf. on Information, Communications & Signal Processing, 2007, pp. 1-4.
[7] M. Taromaru, N. Ando, T. Kodera, and K. Yano, “An EER Transmitter Architecture with Burst-Width Envelope Modulation Based on Triangle-Wave Comparison PWM,” in Proc. IEEE Symp. Personal Indoor and Mobile Radio Communications, 2007, pp. 1-5.
[8] J. H. Chen, H. S. Yang, and Y. J. E. Chen, “A Technique for Implementing Wide Dynamic-Range Polar Transmitters,” IEEE Trans. on Microw. Theory and Tech., vol. 58, no. 9, pp. 2368-2374, Sept. 2010.
[9] J. H. Chen, H. S. Yang, and Y. J. E. Chen, “A Multi-Level Pulse Modulated Polar Transmitter Using Digital Pulse-Width Modulation,” IEEE Microw. Wireless Compon. Lett., vol. 20, No. 5, pp. 295-297 , May 2010.
[10] J. H. Chen, H. S. Yang, H.C. Lin, and Y. J. E. Chen, “A Polar-Transmitter Architecture Using Multiphase Pulse-width Modulation,” IEEE Trans. Circuits and Syst. I. Reg. Papers, vol. 58, no. 2, pp. 244-252, Feb. 2011.
[11] C.H. Kuo, S.L. Liao, “An All-Digital ΔΣ Envelope Modulator for EER-Based on CMOS Standard Cell Design,” in Proc. The 9th IEEE NEWCAS Conf., Bordeaux, Jun. 2011, pp. 325-328.
[12] SAW/FBAR Devices, Datasheet, FAR-F5KA-836M50-D4DF, V2.1b, TAIYO YUDEN CO., LTD., Tokyo, Japan, Mar. 2010.
[13] M. Park, M. H. Perrott, and R. B. Staszewski “An ampulitude resoluation improvement of an RF-DAC employing pulsewith modulation,” IEEE Trans. Circuit Syst. I, Reg. Papers, vol. 58, no. 1, pp. 2590–2063, 2011.
[14] E. M. Umali, S. Yokozawa and Y. Yamao, “Quantization Noise Suppression for Envelope Pulse-Width Modulation (EPWM) Transmitters,” in Proc. IEEE VTC Fall, 2010, pp. 1-5.
[15] E. R. Kretzmer, “Distortion in pulse-duration modulation,” Proc. IRE, vol. 35, no. 11, pp. 1230-1235, Nov. 1947.
[16] L.J L, Y.C Kuo and W.C Cheng ,“Analog PWM and Digital PWM Controller IC for DC/DC Converters,” Innovative Computing, Information and Control (ICICIC), Dec 2009, pp. 904-907.
[17] A. Syed, E. Ahmed, D. Maksimović, and E. Alarcon, “Digital Pulse Width Modulator Architectures,” in Proc. IEEE PESC’04, Conf., 2004, pp. 4689 - 4695.
[18] W. Gu-Yeon and M. Horowize, “A low power switching power supply for self-clocked system.” in Proc. Int. Symp. Low power Electron. Des., 1996, pp. 313-317.
[19] A. P. Dancy and A. P. Chandrakasan, “Ultra low power control circuits for PWM converter,” in Proc. IEEE PESC Conf., 1997, pp.21-27.
[20] A. V. Peterchev, J. Xiao, S. R. Sanders, "Architecture and IC implementation of a digital VRM controller," IEEE Trans. on Power Electron., vol. 18, no. 1, pp. 356-364, Jan. 2003.
[21] Huey Chian Foong, Meng Tong Tan and Yuanjin Zhang, “A Supply and Process-Insensitive 12-bit DPWM for Digital DC-DC Converters,” in Proc. IEEE MWSCAS, 2009, pp. 929-932.
[22] B. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller IC for DC-DC converters,” IEEE Trans. on Power Electron., vol. 18, no. 1, pp. 438–446, Jan. 2003.
[23] H. Chen, S. Li, Q. Niu, Y. Wu and F. Zhou, “A multi-phase self-sensing clock generator for hybrid DPWM application,” in Proc. IEEE ASIC’07, Conf., 2007, pp. 653-638.
[24] O, Trescases, G.Wei, and W.T. Ng, “A segmented digital pulse width modulator with self-calibration for low-power SMPS,” in Proc. IEEE Electron Devices Solid-State Circuit, 2005, pp. 367-p370.
[25] M. G. Batarseh, Wisam AI-Hoor, Lilly Hung, Chris Iannello and Issa Batarseh, “Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulse width Modulator Technique,” IEEE Trans. on Power Electronics, vol. 24, no. 11, pp. 2649-2660, Nov. 2009.
[26] D. Navarro, O. Luc´ıa, L. Barrag´an, J. Artigas, I. Urriza, and O. Jim´enez, “Synchronous FPGA-based high-resolution implementations of digitalpulse-width modulators,” IEEE Trans. on Power Electron., vol. 27, no. 5, pp. 2515–2525, May 2012.
[27] C. H. Kuo and C. D. Jhang, “A Center-Aligned Digital Pulse-Width Modulator for Envelope Modulation of Polar Transmitters,” in Proc. IFIP/IEEE VLSI-SoC, Oct. 2013, pp.386 - 389.
[28] C. H. Kuo and Y. C. Ma, “A 128-phase Delay-Locked Loop with Cyclic VCDL,” Symp. Quality Electronic Design, Penang, Aug 2013, pp. 10-13.
[29] T. Y. Wang, S. M. Lin, and H. W. Tsao, “Multiple Channel Programmable Timing Generators with Single Cyclic Delay Line,” IEEE Trans. on Instrumentation and Measurement, vol. 53, no. 4, pp. 1295 – 1303, Aug 2004.
[30] J. Yuan and C. Seven, “Fast CMOS nonbinary divider and counter,” Electronics Letter, pp. 1222-1233, June 1933.
[31] T. Garbolino, A. Hławiczka, A. Kristof, “Fast and Low-Area TPGs based on T-type Flip-Flops can be Easily Integrated to the Scan Path,”in Proc. IEEE Eur. Test Workshop. ETW, 2000, pp. 161-166.
[32] J. Yuan, C. Svensson, “New TSPC latches and flipflops minimizing delay and power,” in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1996, pp. 160-161.
[33] P. K. Chen, T. K. Chen, H. T. Hu, Y. U. Peng and Y. J. Chen, “A digital pulse width modulator based on pulse shrinking mechanism,” in Proc. IEEE Power Electronics and Drive Systems Int. Conf. PEDS, Nov 2009, pp. 833 - 836.
[34] X. Wang, X. Zhou, J. Park, and A. Q. Huang, “Design and implementation of a 9-bit 8MHzDPWM with AMI06 process,” in Proc. IEEE Appl. Power Electron. Conf. Expo., 2009, pp. 540–545.
[35] X. Wang, X. Zhou, J. Park, and A. Q. Huang, “Analysis of Process-Dependent Maximal Switching Frequency, Choke Effect, and Its Relaxed Solution in High-Resolution DPWM,” IEEE Trans. on Power Electronics, vol. 25, no. 1, pp.152-157, Jan 2001.
[36] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, “Digital Integrated Circuits: A Design Perspective, 2nd edition,” Prentice Hall, 2002.
[37] 劉深淵, 楊清淵, “鎖相迴路,” 滄海書局, Nov. 2006.
[38] 廖述立, Design and Implementation of the Envelope Delta-Sigma Modulator for Multi-Mode Polar-Transmitters, 國立臺灣師範大學應用電子科技研究所碩士論文, 2012.
[39] 馬瑜傑, Design and Implementation of DLL-based PWM for Envelope Modulation of Polar Transmitters, 國立臺灣師範大學應用電子科技研究所碩士論文, 2014.