設計並製作出一個Cross-point記憶體開關來整合於RRAM中，由於記憶體發展的趨勢為高密度、低耗能，而控制電晶體(一般來說是MOSFET)當需要減少元件的大小的時候將面臨問題，平面MOSFET的問題將妨礙記憶體的發展，因此考慮將平面結構發展成三維堆積的結構。
在製程上為求與RRAM上有最佳之相容性，傳統電晶體因製成溫度高，可能導致記憶體之良率下降，故選擇低溫製程之MIM結構並製作出元件,在目前製作出的元件能量測的，且MIM在VON在4V情況下，面積下最大寫入電流Iwrite電流密度約可達，且在絕緣層SiN厚度下在Sneak Path Leakage Effect中電流在寫入電壓Vwrite和Vwrite/2的比值已經達到，且MIM1比值可達，在實際的整合上，寄生電阻扣除後電流在Sneak Path Leakage Effect的比值會更高，目前已把NPN結構與RRAM記憶體結合，未來目標與MIM整合將可提高此二極體的功能性及實用性，可成為未來高密度之3D非揮發性記憶體之控制單元。

In this project, we will design and fabricate a switch for cross-point RRAM applications, since the trend of the development for non-volatile memory is high density, low power consumption. The select devices have the issue for high density memory due to planar structure such as MOSFET. Therefore, the 3D structure will be a candidate for next generation NVM.
In the process, in order to have the best compatibility with RRAM, because of traditional transistors made of high temperature, the yield may lead to memory decline, so choose low-temperature process of MIM structure and produce components. The minimum size for our technology node with devices realized. And in the case of Von in the maximum Ion current density in the areacan up to, and the thickness of the insulating SiN layer the ratio of Vwrite current and Vwrite/2 current has reached, MIM1 device can reach 103. In the actual integration, after allowing for the parasitic resistance in the Sneak Path Leakage Effect current ratio will be higher. We Integrate NPN structure with RRAM to array is working now, and our future work is that integrate NPN structure with RRAM to higher the usability, we look for the high functionality and density for the 3D non-volatile memory with this select device

[1] A.Wang and W. D. Woo, “Static Magnetic Storge and Delay Line,” J. Appl. Phys., 21, 49, 1950
[2] D. Kahng and S. M. Sze, “A Floating Gate and its Application to Memory Device,” Bell Syst.. Tech. J., 46, 1288, 1967
[3] S. M. Sze, “The Floating-Gate Non-Volatile Semiconductor Memory – From Invention to the Digital Age,” International Symposium Nonvolatile Memory – the Technology Driver of the Electronics Industry, NCTU, Hsinchu, Taiwan, 2012
[4] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi and A. Nitayama, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” in VLSI. Tech. Dig., pp. 14-15,2007.
[5] R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, Z. Li, Y. Iwata, R. Kirisawa, H. Aochi, A. Nitayama, “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” in VLSI. Tech. Dig., pp. 136 – 137,2009.
[6] J. Jang, H–S. Kim, W. Cho, H. Cho, J. Kim, Sun Il Shim, Y. Jang, J-H. Jeong, B-K. Son, D-W. Kim, K. Kim, J-J. Shim, J-S. Lim, K-H. Kim, S-Y. Yi, J-Y. Lim, D. Chung, H-C. Moon, S. Hwang, J-W. Lee, Y-H. Son, U-I. Chung and W-S. Lee, “Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory,” in VLSI. Tech. Dig., pp. 192 – 193, 2009.
[7] J. Kim, A-J. Hong, S-M. Kim, E.B. Song, J. H. Park, J. Han, S. Choi, D. Jang, J-T. Moon, and K.L .Wang, “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive),” in VLSI. tech. Dig., pp.186-187,2009
[8] L. Zhang, R. Huang, A.Z.H. Wang, D. Wu, R. Wang, Y. Kuang, “The parasitic effects induced by the contact in RRAM with MIM structure,” in Solid-State and Integrated-Circuit Technology (ICSICT 2008), pp. 932 – 935, 2008.
[9] M.-J. Lee, Y. Park, B.-S. Kang, S.-E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.-H. Lee, S.-J. Chung, Y.-H. Kim, C.-S. Lee, J.- B. Park, I.-G. Baek and I.-K. Yoo, “2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications,” IEDM, p 771, 2007
[10] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura and K. Torii, “Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode,” VLSI, p24, 2009
[11] F. Pellizzer, A. Benvenuti, B. Gleixner, Y. Kim, B. Johnson, M. Magistretti, T. Marangon, A. Pirovano, R. Bez, G. Atwood, “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications,” VLSI, 2006
[12] J.H. Oh, J.H. Park, Y.S. Lim, H.S. Lim, Y.T. Oh, J.S. Kim, J.M. Shin, J.H. Park, Y.J. Song, K.C. Ryoo, D.W. Lim, S.S. Park, J.I. Kim, J.H. Kim, J. Yu, F. Yeung, C.W. Jeong, J.H. Kong, D.H. Kang, G.H. Koh, G.T. Jeong, H.S. Jeong, and Kinam Kim, “Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology,” IEDM, 2006
[13] Y. Zhang, S. Kim, J. P. McVittie, H. Jagannathan, J. B. Ratchford, C. E. D. Chidsey, Y. Nishi, and H.-S. Philip Wong, “An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory,” VLSI, 2007
[14] M. H. Lee, C.-Y. Kao, C.-L. Yang, Y.-S. Chen, H. Y. Lee, F. Chen, and M.-J. Tsai,” Reliability of Ambipolar Switching Poly-Si Diodes for Cross-Point Memory Applications,” DRC Dig., p. 89, 2011..
[15] S.-S. Sheu, P.-C. Chiang, W.-P. Lin, H.-Y. Lee, P.-S. Chen, Y.-S. Chen, T.-Y. Wu , F. T. Chen, K.-L. Su, M.-J. Kao, K.-H. Cheng, M.-J. Tsai, “A 5ns Fast Write Multi-Level Non-Volatile 1 K bits RRAM Memory with Advance Write Scheme,” VLSI, p82, 2009
[16] J. Shin, I. Kim, J. Park, J. Lee, M. Jo, K.P. Biju, S. Jung, W. Lee, S. Kim, S. Park, D. Lee, and H. Hwang, “Effect of MIM type selection device on readout margin of cross-point bipolar ReRAM,” SSDM, 2010
[17] C.-W. Kuo , J.-J. Huang , W.-C. Chang, T.-H. Hou, “One-Diode-One-Resistor Titanium-Oxide RRAM Fabricated at Room Temperature,” SSDM, 2010
[18] C-W. Hsu, J-J. Huang, Y-M. Tseng, T-H. Hou, W-H. Chang, W-Y. Jang, and C-H. Lin,” Flexible One Diode-One Resistor Crossbar Resistive-Switching Memory,” SSDM, F8-3,2011
[19] V. S. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, and Udayan Ganguly, “Punchthrough-Diode-Based Bipolar RRAM Selector by Si Epitaxy,” EDL, vol 33, No.10, 2012
[20] A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, K. Tanabe, T. Nakamura, Y. Sumimoto, N. Yamada, N. Nakai, S. Sakamoto, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Origasa, K. Shimakawa, T. Takagi, T. Mikawa, and K. Aono, “An 8 Mb multilayered cross-point ReRAM macro with 443 MB/s write throughput,” in Proc. IEEE ISSCC Tech. Dig. Papers, pp. 432–434, 2012
[21] M. Son, J. Lee, J. Park, J. Shin, G. Choi, S. Jung,W. Lee, S. Kim, S. Park, and H. Hwang, “Excellent selector characteristics of nanoscale VO2 for high-density bipolar ReRAM applications,” EDL, vol. 32, no. 11, pp. 1579–1581, Nov. 2011.
[22] W. Lee, J. Park, J. Shin, J. Woo, S. Kim,G. Choi, S. Jung, S. Park, D. Lee, E. Cha, H.D. Lee, S.G. Kim, S. Chung and H. Hwang, “Varistor-type Bidirectional Switch (JMAX>107A/cm2, Selectivity~104) for 3D Bipolar Resistive Memory Arrays,” VLSI, p.37, 2012
[23] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, C. H. Lien, and M.-J. Tsai,“ Low Power and High Speed Bipolar Switchingwith A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM, “ IEDM Tech. Dig., p. 297, 2008.
[24] Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin, W. H. Liu, Y. Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen, C. H. Lien, and M.-J. Tsai,” Highly Scalable Hafnium Oxide Memory with Improvements of Resistive Distribution and Read Disturb Immunity,” IEDM Tech. Dig., p. 105, 2009
[25] J. Shin, I. Kim, K.P. Biju, M. Jo, J. Park, J. Lee, S. Jung, W. Lee, S. Kim, S. Park, and H. Hwang,” TiO2-based metal-insulator-metal selection device for bipolar resistive random access memory cross-point application,” JAP, 109, p. 033712, 2011.
[26] J-J. Huang, Y-M. Tseng, W-C. Luo, C-W. Hsu, and T-H. Hou,” One Selector-One Resistor (1S1R) Crossbar Array for High-density Flexible Memory Applications,” IEDM Tech. Dig., p. 733, 2011.
[27] R. S. Shenoy, K. Gopalakrishnan, B. Jackson, K. Virwani, G. W. Burr, C. T. Rettner, A. Padilla, D. S. Bethune, R. M. Shelby, A. J. Kellock, M. Breitwisch, E. A. Joseph, R. Dasaka, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi,” Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint-Memory based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials,” in VLSI Symp. Tech. Dig., p. 94, 2011.
[28] E. Linn, R. Rosezin, C. Kügeler and R.Waser,“ Complementary resistive switches for passive nanocrossbar memories, “ Nature Mater., 9, p. 403, 2010.
[29] Y-S. Chen, H-Y. Lee, P-S. Chen, P-Y. Gu, W-H. Liu, W-S. Chen, Y-Y. Hsu,.C-H. Tsai, F. Chen, M-J. Tsai, and C. Lien., “Good Endurance and Memory Window for Ti/HfOx Pillar RRAM at 50-nm Scale by Optimal Encapsulation Layer,” EDL, 32, p. 390, 2011
[30] T. Li , et al , US.Patent NO: 2009/0032817