簡易檢索 / 詳目顯示

研究生: 趙家祥
Chia-Hsiang Chao
論文名稱: 應用於X頻帶9.75/10.6 GHz頻率合成器之設計與實現
Design and Implementation of X-band 9.75/10.6GHz Frequency Synthesizer
指導教授: 蔡政翰
Tsai, Jen-Han
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 129
中文關鍵詞: X頻段頻率合成器交叉耦合對電壓控制振盪器多模除頻器9.75/10.6GHz LNB
英文關鍵詞: X-band, Frequency Synthesizer, Cross-coupled pair VCO, Multi-Modulus Divider, 9.75/10.6GHz LNB
論文種類: 學術論文
相關次數: 點閱:357下載:18
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在數位傳播衛星(DBS)的規範下,操作在Ku頻帶10.7~12.75GHz的低雜訊模塊降頻器是衛星電視訊號接收鏈中一個重要的部份。因為低雜訊模塊降頻器必需將Ku-Band的RF訊號降頻至L-Band的IF訊號(0.95~2.15GHz)。因此在低雜訊模塊降頻器的設計上,需要一個X頻帶頻率合成器來提供9.75GHz及10.6GHz的振盪源訊號。本論文使用了TSMC CMOS 0.18-µm製程實現了X頻段9.75/10.6GHz頻率合成器。
    本論文依序實現了多模除頻器、X頻帶頻率合成器前端電路以及X頻帶9.75/10.6GHz頻率合成器,分別在第三章、第四章及第五章呈現。在第三章實現出了一個七位元多模除頻器,其除數從128~255,在直流偏壓1.5V下最高可操作在3.3GHz,功率消耗為5.85mW。在第四章實現了X頻帶頻率合成器前端電路,包含電壓控制振盪器及除四預除頻器電路兩個部份。電壓控制振盪器部份採用交叉耦合對的方式,同時利用一個開關電路來實現9.75/10.6 GHz頻段切換的功能。其功率消耗為10.5mW。高頻頻段相位雜訊在載波偏移1MHz處-102.95dBc/Hz;低頻頻段相位雜訊在載波偏移1MHz處為-92.199dBc/Hz。預除頻電路部分採用電流模式邏輯式的除頻器架構。同時,刪除了CML的尾電流部分來增加速度。其功率消耗為14.5mW。在第五章實現了X頻帶9.75/10.6GHz頻率合成器。輸出頻率為9.75GHz時,相位雜訊在載波偏移100KHz處為-66.11 dBc/Hz;在載波偏移1MHz處為-89.85 dBc/Hz。輸出頻率為10.6GHz時,相位雜訊在載波偏移100KHz處為-66.77 dBC/Hz;在載波偏移1MHz處為-90.55 dBC/Hz。其功率消耗為34.5mW。

    Under Digital Broadcast Satellite (DBS) regulations, Low Noise Block (LNB) down-converter operated in Ku-band 10.7~12.75 GHz is an important part of the satellite- TV reception chain. Because LNB down-converter is in charge of converting the Ku-band RF signal down to L-band IF signal (0.95~2.15GHz), the X-band frequency synthesizers is necessary block in LNB system design to provide 9.75GHz and 10.6GHz local oscillator (LO). In this thesis, a X-band 9.75/10.6 GHz Frequency Synthesizer is presented by using TSMC CMOS 0.18-µm process.
    This thesis implemented 7-bits Multi-Modulus Divider, X-band synthesizer frontend circuit and X-band 9.75/10.6 GHz frequency synthesizer in chapter 3, chapter 4 and chapter 5, respectively. In chapter 3, 7-bits Multi-Modulus Divider is presented, which divisor are 128~255 and highest operating frequency is 3.3 GHz in 1.5V.Multi-Modulus divider power consumption is 5.85 mW. In chapter 4, X-band synthesizer frontend circuit, included VCO and ÷4 prescalar, is presented. The VCO employs LC-tank cross-coupled pair architecture. In order to switch frequencies between the 9.75 GHz and 10.6 GHz, VCO specially use a switch circuit. VCO power consumption is 10.5 mW. When VCO in high band, phase noise is -102.95 dBc/Hz@1MHz. In low band, phase noise is -92.19 dBc/Hz@1MHz. The ÷4 prescalar circuit employs CML architecture. For promoting the speed, tail-current of CML Divider are removed.CML power consumption is 14.5 mW. In chapter 5, X-band 9.75/10.6 GHz frequency Synthesizer is presented. When output frequency in 9.75 GHz, phase noise are -66.11 dBc/Hz@100KHz and -89.85 dBc/Hz@1MHz. When output frequency in 10.6 GHz, phase noise are -66.77 dBc/Hz@100KHz and -90.55 dBc/Hz@1MHz. X-band Frequency Synthesizer power consumption is 34.5mW.

    中文摘要……………………………………………………………………i ABSTRACT………………………………………………………………………iii 誌  謝……………...…………………………………………………………...v 目  錄…………………………………………………………………………vii 圖 目 錄…………………………………………….……………………………xi 表 目 錄………………………………………………………………………xvii 第一章  緒論……………………………………………………………………1 1.1 研究背景及動機………………………………………………………1 1.2 現況探討………………………………………………………………2 1.3 研究成果....................…………………………………………………4 1.4 論文架構…………………………………………………….………...5 第二章  鎖相迴路的基本觀念…………………………………………………7 2.1 相位頻率偵測器.……………………………………………………8 2.2 充電泵……………………….…………..…………………………11 2.3 迴路濾波器…..…………….…………..……………………………17 2.4 頻率除頻器…..…………….…………..……………………………18 2.5電壓控制振盪器………….…………..……………………………19 2.6 鎖相迴路分析...…………….…………..……………………………20 2.6.1 鎖相迴路系統分析..………………..…………………………..20 2.6.2 Spur分析...……….……………….…………………………..26 第三章  應用於頻率合成器之多模除頻器設計與實現……………………29 3.1 多模除頻器簡介..…………………………………………………29 3.2 七位元可程式化多模除頻器之設計.……………………………31 3.2.1 靜態除頻器...…………………………………………………31 3.2.2 脈波吞噬型除頻器……………………………………………..32 3.2.3 可程式化多模除頻器之架構…………………………………..33 3.2.4 除2/3除頻器(Divide-by-2/3 Cell )之設計…………………..35 3.3 七位元可程式化多模除頻器之電路模擬…………………………39 3.4 七位元可程式化多模除頻器之電路量測結果……………………42 3.5 結果與討論………………………………………………………46 第四章  X頻帶頻率合成器的前端電路設計……………………....……...…49 4.1 電壓控制振盪器簡介.…………………..…………………………50 4.1.1 電壓控制振盪器設計重點……………..……………………..50 4.1.2 巴克豪森準則……………….………………………………..51 4.1.3 環形振盪器與LC振盪器…………………………………..52 4.2 交叉耦合對LC振盪器分析..………….……………………..…53 4.2.1 巴克豪森準則分析…..………………………………………..53 4.2.2 負電阻分析……………………………………………………..55 4.3 相位雜訊……………………………………………………………56 4.3.1 相位雜訊定義………………………………………………..56 4.3.2 Lesson’s Model 相位雜訊模型….………………………..59 4.3.3 相位雜訊的影響………………………………………………..61 4.4  LC振盪器的被動元件……………………………………………61 4.4.1 電感…………………………….……………………………..61 4.4.2 變容器………………..………………………………………..63 4.5 變壓器回授壓控振盪器設計………………………………………64 4.5.1 雙頻段變壓器回授式壓控振盪器架構………………………..65 4.5.2 變壓器與變容器的模擬….…………………………………..66 4.5.3 變壓器回授式壓控震盪器模擬結果….……………………..70 4.6  X頻帶除四預除頻器…..…………………………………………73 4.7  X頻帶頻率合成器前端電路之整合….……………………………74 4.8 量測結果..…………………………………………………………76 4.9 結果與討論…………………………………………………………81 第五章  X頻帶9.75/10.6 GHz頻率合成器之設計與實現……….………..87 5.1 簡介…………………………………………………………………87 5.2 電路架構與規格……………………………………….....……...…84 5.3 相位頻率偵測器……………………………………………………91 5.4 充電泵………………………...……………………………………93 5.5 三階濾波器………………………………………………………….94 5.6 電壓控制振盪器….….………………………………………………96 5.7 除頻鏈………………………………………………………………99 5.8 電路模擬….………………………………………………………100 5.8.1 頻率合成器系統模擬………………………………….101 5.8.2 頻率合成器相位雜訊模擬….….……...………………..104 5.9  X頻帶頻率合成器的量測方式及結果……….…………………108 5.10 結果與討論………………………………………………………117 第六章  結論………………………………………………………….….…123 參考文獻……………………………………………………………………….125 自傳……………………………………………………………………….129

    [1] 虞孝成,唐震寰,杭學銘,張成軍, 衛星廣播電視工程技術與規範, 交通部電信總局,民國87年, http://ir.lib.nctu.edu.tw/handle/987654321/12933。
    [2] S. Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi and H. K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 691-700, May 1997
    [3] G. Wegmann, E. A. Vittoz, and F. Rahali, “Charge injection in analog MOS switches,” IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 1091-1097, Dec. 1987.
    [4] Bing J. Sheu and Chenming Hu, “Switch-induced error voltage on a switched capacitor,” IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 519-525, Aug. 1984.
    [5] Woogeun Rhee, “Design of high performance CMOS charge pump in phase locked loop,” in Proc. IEEE Int. Symp. Circuits and Systems, 1999, pp. 545-548.
    [6] Mark Van Paemel, “Analysis of a charge-pump PLL: A new model,” IEEE Trans. Commun., vol. 42, no.7, pp. 2490-2498, July 1994.
    [7] F. M. Gardner, “Charge-pump phase-lock loops,“ IEEE Trans. Commun., vol. 28, no. 11, pp. 1849-1858, Nov. 1980.
    [8] William O. Keese, “An analysis and performance evaluation of a passive filter design techniques for charge pump PLL’s,” National Semiconductor application note 1001, July 2001.
    [9] 劉深淵, 鎖相迴路, 滄海書局, 2006.
    [10] J. Yuan, and C. Svensson, “High speed CMOS circuit technique,” IEEE J. of Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
    [11] T. Mohsen, “Design of a PLL based frequency synthesizer for WiMAX applications,” 18th Iranian Conference on Electrical Engineering (ICEE), Isfahan, Iran, May 2010, pp. 377–381
    [12] S.-C. Tseng, C. Meng, S. Y. Li, J. Y. Su, and G. W. Huang, “2.4 GHz divide-by-256∼271 single-ended frequency divider in standard 0.35-μm CMOS technology,” in Proc. Asia-Pacific Microwave Conference, 2005, vol.2, p. 4.
    [13] M. Jung, “A 10 GHz low-power multi-modulus frequency divider using Extended True Single-Phase Clock (E-TSPC) Logic,” 7th European Microwave Integrated Circuits Conference, Amsterdam, Oct. 2012, pp. 508-511
    [14] C.-S. Lin, C.L. Wey, Y.-Z Juang, C.M. Huang, “High-speed and low-power programmable frequency divider,” Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, June 2010, pp. 4301-4304
    [15] J.-H. Tsai, Y.-W. Chung, H.-D. Shih, J.-P. Chou, “A 7–12 GHz multi-modulus frequency divider,” Asia-Pacific Microwave Conference Proceedings, Kaohsiung, Dec. 2012, pp. 1232 – 1234
    [16] Behzad Razavi, 類比積體電路設計, 李泰成, 滄海書局, 2010
    [17] Ali Hajimiri, and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
    [18] Behzad Razavi, RF Microelectronics Second Edition, Los Angeles: Pearson, 2013.
    [19] D. B. Leeson, “A simple model of feedBack oscillator noise spectrum,” Proc. IEEE, vol. 54, pp. 329-330, Feb. 1966.
    [20] C. Patrick Yue, and S. Simon Wang, “On-chip spiral inductors with patterned ground shields for Si-based RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, no.5, pp. 743-752, May 1998.
    [21] Pietro Andreani and Sven Mattisson, “On the use of MOS varactors in RF VCOs ,” IEEE J. of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
    [22] Pietro Andreani and Sven Mattisson, “On the use of MOS varactors in RF VCOs, ” IEEE J. of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
    [23] KaChun Kwok, and Howard C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedBack,” IEEE J. of Solid-State Circuits, vol. 40, no. 3, pp. 652-660, Mar 2005.
    [24] P. Payandehnia., H. Maghami, “High speed CML latch using active inductor in 0.18μm CMOS technology,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, May 2011, pp. 1-4.
    [25] To-Po Wang, Chung-Chin Li, “A 0.4-V 1.08-mW 12-GHz high-performance VCO in 0.18-µm CMOS,” 2012 IEEE Radio and Wireless Symposium, Santa Clara, CA, Jan. 2012, pp. 207-210
    [26] W. De Cock, M. Steyaert, “A CMOS 10GHz voltage controlled LC-oscillator with integrated high-Q inductor,” Proceedings of the 27th European Solid-State Circuits Conference, Villach, Austria, Sept. 2001, pp. 498 – 501
    [27] H.Z. Wang, “An area-efficient 5GHz/10GHz dual-mode VCO with coupled helical inductors in 0.13-UM CMOS technology,” 24th Canadian Conference on Electrical and Computer Engineering, Niagara Falls, May 2011, pp.512-515
    [28] N. Seller, “A 10GHz Distributed Voltage Controlled Oscillator for WLAN Application in a VLSI 65nm CMOS Process,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Honolulu, June 2007, pp. 115-118
    [29] 泰藝電子, http://www.taitien.com.tw/cht/products_crystal.aspx, 產品規格書。
    [30] P. Philippe, S. Bardy, S. Wane, F. Moreau, E. Thomas, L. Praamsma, “A low power 9.75/10.6GHz PLL in SiGe BiCMOS for Ku-band satellite LNBs,” 41st European Microwave Conference, Manchester, Oct. 2011, pp. 1130-1133
    [31] J.G Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, vol. 31, pp.1723-1732, Nov. 1996
    [32] Cheng Zhang, M. Syrzycki, “A high performance NMOS-switch high swing cascode charge pump for phase-locked loops,“ IEEE 55th International Midwest Symposium on Circuits and Systems, Boise, Aug. 2012, pp. 554-557
    [33] Z. Brezović, V. Kudjak, “PLL phase-noise modeling by PC,” 19th International Conference, Bratislava, April 2009, pp. 195-198
    [34] L. Dickstein, http://www.gigatronics.com/uploads/document/AN-GT140A- Introduction-to-Phase-Noise-in-Signal-Generators.pdf, pp.4.
    [35] E. Suijker, L. de Boer, G. Visser, “Integrated X-band FMCW front-end in SiGe BiCMOS,” European Microwave Conference, Paris, Sept. 2010, pp. 1082-1085
    [36] N. Pavlovic, J. Gosselin, K. Mistry, “A 10 GHz frequency synthesiser for 802.11a in 0.18 μm CMOS,” Proceeding of the 30th European Solid-State Circuits Conference, Sept. 2004, pp. 367-370
    [37] T.-H. Lin, Yu-Jen Lai, “An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL,” IEEE Journal of Solid-State Circuits, vol.42, no.2, pp. 340-349, Feb. 2007
    [38] 施宏達, “應用於X頻段之鎖相迴路與頻率合成器之實現與設計,” 國立台灣師範大學應用電子科技學系研究所碩士論文, 民國一百零一年
    [39] J.-Y. Lee, J.K. Kwon, “A 9.1-to-11.5-GHz Four-Band PLL for X-Band Satellite & Optical Communication Applications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Honolulu, June 2007, pp. 233-236
    [40] 周建平, “低功率鎖相迴路與電壓控制振盪器之設計與實現,” 國立台灣師範大學應用電子科技學系研究所碩士論文, 民國一百零二年

    下載圖示
    QR CODE