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研究生: 古翔升
Gu, Siang-Sheng
論文名稱: 鐵電負電容效應之奈米片環繞式電晶體
Nanosheet GAA(Gate-All-Around) Transistors with Ferroelectric Negative Capacitance Effect
指導教授: 李敏鴻
Lee, Min-Hung
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2018
畢業學年度: 106
語文別: 中文
論文頁數: 71
中文關鍵詞: 陡峭次臨界電晶體奈米片電晶體鐵電材料
英文關鍵詞: Steep subthreshold swing, Nanosheet transistor, Ferroelectric material
DOI URL: http://doi.org/10.6345/THE.NTNU.EPST.005.2018.E08
論文種類: 學術論文
相關次數: 點閱:174下載:0
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  • 鰭式電晶體廣泛應用在許多3C產品中,例如:手機iPhoneA9處理器、電腦IC晶片……等,而在未來製程節點中,改善次臨界擺幅SS(Subthreshold Swing)降低元件之操作電壓與功率極為重要,本論文藉由導入HfZrO2鐵電材料當作電晶體的介電層,應用鐵電材料之負電容效應改善次臨界擺幅(SS)。
    近期IBM團隊提出奈米片結構電晶體(Nanosheet FET),有別於鰭式電晶體,奈米片電晶體是參考Gate-All-Around(GAA)電晶體結構, Si通道設計成水平的結構,可有效解決鰭式電晶體鰭高的製程瓶頸,並廣泛應用在各大領域中,例如:人工智慧(AI)、虛擬實境(VR)……等,本論文是以鐵電材料HfZrO2作為介電層,應用於奈米片電晶體中,達到俱有鐵電負電容效應之奈米片電晶體,其中黃光製程部分皆使用I-line步進機,可以提高生產效率。

    FinFET transistors were used in many 3C products, e.g., iPhoneA9 CPU, GPU and Bitcoin Mining Hardware. Moreover, the improvement of SS(Subthreshold Swing) may reduce driving voltage and power consumption in next-generation technology node. In this work, the super steep subthreshold swing is obtained by NC effect using HfZrO2 for dielectric.
    The IBM group proposed the Nanosheet GAA FET which is a Fin-like in horizontal. The Si channel were designed a horizontal direction, and solve process difficult of the Fin height in the FinFET process. The application are such as AI, VR, …e.g. This work is used Ferroelectric HfZrO2 as Gate for NS-GAA Transistors. The Lithography process is employed 365nm I-line stepper with self-alignment and cost down.

    Publications I 中文摘要 II Abstract III 致謝 IV 目錄 V 圖目錄 VIII 表目錄 XII 第一章 簡介與文獻探討 1-1 鐵電材料-鉿基氧化物與負電容效應文獻探討 1 1-2 鰭式電晶體文獻探討 4 1-3 奈米片電晶體文獻探討 7 第二章 n與p型鐵電負電容先閘極電晶體 2-1 實驗動機 10 2-2 n與p型鐵電負電容先閘極電晶體製程 12 2-2-1 元件清洗與沈積HKMG 12 2-2-2 金屬薄膜製程與黃光製程 15 2-2-3 蝕刻與離子佈植 16 2-3 n與p型MOSFET HfZrO2 5nm與7nm電性分析 18 2-4 HfZrO2之GI-XRD材料分析 20 2-5 結論 22 第三章 SOI之單層奈米片製作(Nano sheet) 3-1 實驗動機 23 3-2 薄型光阻用於I-line黃光微影與曝光劑量測試 25 3-3 乾式蝕刻trimming薄光阻 27 3-4 水平爐管熱氧化消耗奈米片線寬 32 3-5 奈米片SOI 與 Bulk Si線寬比較 34 3-6 結論 36 第四章 鐵電負電容效應之奈米片電晶體 4-1 實驗動機 37 4-2 鐵電負電容效應之奈米片電晶體製作流程 39 4-2-1 SOI晶圓前置作業 39 4-2-2 奈米片之黃光製程 42 4-2-3 奈米片高製作與熱氧化消耗奈米片線寬 46 4-2-4 上層SiO2去除與沈積HKMG介電層 48 4-2-5 金屬層製程與改良Gate黃光曝光 49 4-3 TEM觀測與電性量測 55 4-3-1 奈米片TEM與 Top View觀測 55 4-3-2 奈米片不同退火溫度之電性量測 60 4-3-3 VG電壓由小至大與多次量測之電性分析 63 4-4 結論 65 第五章 結論與未來工作 5-1 結論 66 5-2 未來工作 67 參考文獻 68

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