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研究生: 曾裕程
Tseng, Yu-Cheng
論文名稱: 系統層級靜電放電防護之瞬態偵測電路
Transient Detection Circuit for System-Level ESD Protection
指導教授: 林群祐
Lin, Chun-Yu
口試委員: 郭建宏
Kuo, Chien-Hung
劉仁傑
Liu, Jen-Chieh
林群祐
Lin, Chun-Yu
口試日期: 2023/12/15
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2024
畢業學年度: 112
語文別: 英文
論文頁數: 76
中文關鍵詞: 靜電放電晶片上瞬態偵測電路電壓過衝
英文關鍵詞: electrostatic discharge (ESD), on-chip transient detection circuit, voltage overshoot
研究方法: 實驗設計法
DOI URL: http://doi.org/10.6345/NTNU202400354
論文種類: 學術論文
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  • 隨著晶片製程的進步,積體電路 (Integrated Circuit, IC) 中的元件尺寸逐漸微縮,導致積體電路除了更容易遭受靜電放電 (Electrostatic Discharge, ESD) 而導致永久性的損毀以外,電壓源電位的下降使得積體電路操作時所受靜電放電、電磁干擾 (Electromagnetic Interference, EMI) 影響的程度也日益提升,因此微電子產品需要確保滿足靜電放電可靠度的規範,同時也必須探討微電子產品因受到靜電放電引起的雜訊等干擾造成的故障問題。
    積體電路中因電磁干擾或靜電放電激發的瞬態時變電流經過寄生元件造成的電壓擾動會形成干擾雜訊,並隨機耦合至微電子產品內電路系統中各個電壓源或端點上,因此即使有防護電路來排放靜電電流避免電子產品毀壞仍然可能出現故障情形,因此多數微電子產品具有瞬態偵測電路來偵測產品是否操作異常,並藉由與韌體、硬體結合的方式,以達到當電子產品發生故障時具備自我重置能力的系統來解決上述產品發生故障的問題。此外,工程師在進行靜電放電問題的除錯時,由於無法具體得知靜電電流的確切路徑與實際的電流值,電路系統中各個元件或端點的電壓與電流值也無法得知,造成在分析電路系統上會十分棘手,但透過在電路系統內部加入瞬態偵測電路能夠在幾乎不影響系統架構下偵測系統中一些關鍵端點的電壓、電流等資訊以提升除錯的效率。
    故本論文提出一種新型偵測電壓源的瞬態偵測電路,並在0.18μm CMOS製程技術下實現,用於偵測電壓源的電位擾動情形,透過量測可以觀察靜電放電對積體電路導致局部範圍干擾程度的情形。此外,特定元件的電壓差發生瞬間變化時可能會有電壓過衝的現象,例如:二極體、金氧半場效電晶體 (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)。該現象可能會造成瞬態偵測電路偵測結果準確度降低的問題,所以本論文亦透過0.18μm CMOS製程技術實現了一種具有元件補償設計方法的瞬態偵測電路,旨在降低偵測電路受到電壓過衝的影響,並用於偵測由 (Input/Output, I/O) 輸入/輸出端所注入的靜電電流值,透過該電路分析電壓過衝影響偵測電路準確度的問題,以及討論是否能夠利用元件補償的方式降低電壓過衝的影響。

    With the advancement of the chip manufacturing process, the dimension of components in integrated circuit (IC) is gradually shrinking, which makes IC more susceptible to irreversible damage caused by electrostatic discharge (ESD). In addition, decreasing voltage supply sources make the IC operation more susceptible to ESD and electromagnetic interference (EMI). Consequently, reliability issues related to ESD become more important, and malfunctions caused by transient disturbances must also be discussed.
    Transient noise caused by transient time-varying currents passing through parasitic elements in the IC through ESD or EMI can cause voltage disturbances, which are randomly coupled to the voltage source or terminal in the circuit system of the microelectronic product. Therefore, even if ESD current could be discharged through ESD protection, it is still possible for microelectronic products to malfunction or be damaged. Thus, most products depend on transient detection circuits to detect whether the product is in an abnormal operating state. Besides, being integrated into IC co-design with firmware and hardware enables the system of microelectronic products to perform self-resetting while the product failure mentioned previously happens. In addition, it is difficult for the engineers to determine the exact path and current value of ESD current, as well as the voltage and current value of each device or terminal in the circuit system while they are debugging ESD issues. As a result, analyzing ESD issues becomes more challenging. However, adding a transient detection circuit to the system allows it to detect the voltage, and current information of important terminals in the system without affecting the system structure, improving the efficiency of debugging.
    In this thesis, a new type of power-rail transient detection circuit was proposed for detecting voltage supplies. The circuit is implemented in 0.18μm CMOS process technology to detect voltage potential disturbances of voltage sources, and the influence of ESD on the local area of IC can be observed through measurement. In addition, instantaneous changes in the voltage potential difference between devices may result in voltage overshoot, potentially reducing the accuracy of the detection circuit. For example, when utilizing a diode or a metal-oxide-semiconductor field-effect transistor (MOSFET), this situation could lead to a reduction in the accuracy of the transient detection circuit's results. Thus, this thesis also realized by 0.18μm CMOS process technology to implement a device compensation design method for detecting ESD current injected from the input/output (I/O) terminal. The impact on the accuracy of the detection circuit for voltage overshoot was analyzed, and whether the influence can be reduced through device compensation was also discussed.

    Chapter 1 Introduction 1 1.1 System-Level ESD Issue for Microelectronic Products 1 1.2 System-Level ESD Test Standard 2 1.3 Solution to Improve the System-Level ESD Immunity 8 1.4 Thesis Organization 9 Chapter 2 Study of Solutions to Overcome Electrical Transient Disturbance 10 2.1 Background of ESD Protection in Microelectronic Products 10 2.2 ESD Protection Design Implementation on Board 11 2.2.1 Printed Circuit Board (PCB) for Enhanced ESD Immunity 12 2.2.2 Low-Pass Noise Filter for ESD Mitigation 12 2.2.3 TVS for System-Level ESD Protection Applications 13 2.3 Hardware/Firmware Co-Design Solutions 15 2.4 Summary of Solutions to Overcome Electrical Transient Disturbance in Microelectronic Products 17 Chapter 3 Design of On-Chip Power-Rail Transient Detection Circuit 18 3.1 Background of On-Chip Power-Rail Transient Detection Circuit 18 3.1.1 Prior Arts 18 3.1.2 Simulation Waveform of System-Level ESD Test 23 3.1.3 Study on the Influence of NCAP Capacitance and Sampling Device Size on the SAH Circuit 24 3.2 Proposed On-Chip Power-Rail Transient Detection Circuit 28 3.2.1 Circuit Implementation 28 3.2.2 HSPICE Simulation Results under System-Level ESD 34 3.3 Measurement Results under System-Level ESD Zapping 42 3.4 Summary of On-Chip Power-Rail Transient Detection Circuit 50 Chapter 4 Design of On-Chip I/O Transient Detection Circuit 52 4.1 Background of On-Chip I/O Transient Detection Circuit 52 4.2 Impact of Voltage Overshoot on Transient Detection Circuit Accuracy 53 4.3 Design of I/O Transient Detection Circuit 54 4.3.1 Circuit Structure 54 4.3.2 HSPICE Simulation Results under System-Level ESD 57 4.4 Measurement Results under Pulse Signal and System-Level ESD Zapping 61 4.5 Summary of On-Chip I/O Transient Detection Circuit 66 Chapter 5 Conclusion and Future Work 67 5.1 Conclusion 67 5.2 Future Work 68 Reference 71 Vita 75 Publication List 76

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