研究生: |
陳建廷 Chien-Ting Chen |
---|---|
論文名稱: |
適用於高速菲涅耳轉換之積體電路架構設計 Efficient VLSI Architecture for Fresnel Transform |
指導教授: |
黃文吉
Hwang, Wen-Jyi |
學位類別: |
碩士 Master |
系所名稱: |
資訊工程學系 Department of Computer Science and Information Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 69 |
中文關鍵詞: | 系統晶片設計 、FPGA 、菲涅耳轉換 |
論文種類: | 學術論文 |
相關次數: | 點閱:157 下載:4 |
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本論文主要提出一硬體架構實現高速菲涅耳轉換,透過本硬體架構可還原全像片的相位值,後續再進行相位展開法則計算即可重建出物體實際樣貌。為了提高精確度,本硬體電路中大多使用IEEE 754浮點數格式進行運算,運算單元內部皆以管線化架構的方式實現,並且利用最佳排程將各運算單元之計算以平行的方式進行,有效提高菲涅耳轉換整體電路的運算效率,最後將此電路實現於FPGA開發平台並實際量測硬體資源消耗、運算時間以及功率消耗,透過硬體運算結果與軟體運算結果相互驗證確認還原結果正確。根據實驗結果,本論文提出之硬體架構有高精確度、高速運算以及低功率消耗之優點,對於現今要求即時運算的嵌入式數位全像系統,本論文所提出之硬體架構較具有競爭力。
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