近幾年來半導體的領域中，鐵電材料與現今CMOS 製程相容，是非常熱門的研究主題，而鐵電氧化鉿鋯(HfZrO2, HZO)也已被廣泛的利用。本論文系統地研究了用於增強（Potentiation）/ 抑制（Depression）機器學習的等脈衝編程，以使用5nm厚的HZO鐵電電晶體實現非線性度（α_P= 1.25和α_D = -3.69）和高電導比率（> 103x）。顯示出電導比率和線性之間的權衡特性。記憶窗（memory window, MW）增強的較高剩餘極化（Pr）將導致電導比率增加，但會降低訓練曲線的線性度。對於HZO厚度從15nm到5nm的HZO，以50ns的脈衝寬度和較低的脈衝電壓執行等脈衝的優化學習條件。這些突出的優點為將來記憶體內計算（computing-in-memory, CIM）應用程序等新興應用提供了機會。
而記憶窗作為主要決定因子，我們也嘗試透過介電層（dielectric, DE）與鐵電層相對位置調變，由量測結果發現上層的DE與下層DE相比有較大的記憶窗，且2階的資料保存能力達103秒無衰退現象，可重複操作次數超過105個cycles。在確立了其元件的特性後，我們嘗試以不同的脈衝條件，令元件達成機器學習的效果。鐵電電晶體的學習曲線具有良好的線性與對稱性。
雙層鐵電電晶體（double-layer ferroelectric, DFE），以改善機器學習中權重更新的非線性。雙層非對稱之FeFET（HZO 5nm / Al2O3 0.5nm / HZO 10nm）具有2.3 V的記憶窗，可操作 >105的耐久性，並可保持 >104秒。FeFET新型極化輔助脫陷阱（polarization assisted de-trapping, PAD）方法，增強型學習曲線的非線性度（αp）可以降低到0.07。

In recent years, ferroelectric materials have attracted growing interest and have been extensively investigated to leverage state-of-the-art CMOS architectures. Identical pulse stimulation for Potentiation/Depression machine learning is investigated systemically to achieve linear (αP = 1.25 and αD = -3.69) and high conductance ratio (>103x) with 5nm-thick HfZrO2 (HZO) FeFET. The trade-off characteristics between conductance ratio and linearity is exhibited. The higher remnant polarization (Pr) for memory window (MW) enhancement would lead increasing conductance ratio, but degrades linearity of training curve. The optimized stimulation condition for identical pulse is performed with pulse width 50 ns and low access voltage for HZO thicknesses from 15 nm down to 5 nm. These highlight merits provide opportunity to integrate emerging devices such as computing-in-memory (CIM) application in the future. We also modulated the ferroelectric layer position through dielectric layer (DE). The data retention >103 sec and endurance >105 cycles are obtained. The deep leaning is also performed by pulse modulation, and the excellent linearity is obtained.
Double-layer ferroelectric (DFE) FeFET is studied for improving the non-linearity of weight update in machine learning. The proposed gate stack (HZO 5nm/ Al2O3 0.5nm/ HZO 10nm) of FeFET exhibits memory window of 2.3 V, resulting in 2 states with the endurance of 105 and the retention of 104 s. Non-linearity fitting parameter (αp) of Potentiation conductance of DFE FeFET by the novel polarization assisted de-trapping (PAD) could be reduced to 0.07.

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