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研究生: 李宗翰
Li, Zong-Han
論文名稱: 鐵電材料於陣列記憶體之製程研究及需求
Research and Requirements of Ferroelectric Materials in Array Memory Fabrication
指導教授: 李敏鴻
Lee, Min-Hung
廖書賢
Liao, Shu-Hsien
口試委員: 李敏鴻
Lee, Min-Hung
廖書賢
Liao, Shu-Hsien
葉凌彥
Yeh, Ling-Yen
口試日期: 2024/07/26
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2024
畢業學年度: 112
語文別: 中文
論文頁數: 50
中文關鍵詞: 鐵電氧化鉿鋯鐵電隨機存取記憶體固態溶解超晶格記憶體陣列
英文關鍵詞: HfxZrxO2(HZO), FeRAM, Memory Array, solid-solution (SS), superlattice (SL)
研究方法: 實驗設計法行動研究法準實驗設計法主題分析
DOI URL: http://doi.org/10.6345/NTNU202401732
論文種類: 學術論文
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  • 伴隨著技術節點的演進,元件尺寸不斷的微縮,電子元件須滿足低功耗、高密度、高效能以及尺寸微縮等特性,鐵電鉿基氧化物因其天然的雙穩態、高速運行和低功耗而在記憶體應用中引起了廣泛關注,嵌入式非揮發性記憶體和存儲級記憶體可以透過積成鐵電氧化鉿鋯來實現鐵電隨機存取記憶體。
    近年來鐵電材料於記憶體領域得到廣泛的研究,由於鉿基氧化物鐵電材料具有與陣列記憶體製程優異的相容性,相比傳統鈣鈦礦的鐵電材料成為新興記憶體的候選者之一。
    本論文研究分為三個部分,第一部份透過台灣半導體中心以及國立陽明交通大學奈米中心提供的機台開發出不同材料厚度的記憶體,第二部分為開發鐵電材料運用於陣列記憶體的製程,第三部分透過原子層沉積系統調變不同前驅物沉積順序,分別開發固態溶解與超晶格之鐵電氧化鉿鋯堆疊製程,並使鐵電層厚度再減薄,達到降低操作電壓效果,超晶格的結構有助於鐵電氧化層的結晶,進階將其應用於記憶體陣列的運用。

    With the evolution of technology nodes, the size of electronic devices continues to shrink, necessitating characteristics such as low power consumption, high density, high performance, and miniaturization. Hafnium oxide-based ferroelectric materials (HfO2) have garnered extensive attention in memory applications due to their inherent bistable states, high-speed operation, and low power consumption. Embedded non-volatile memory (eNVM) and storage-class memory (SCM) can be realized using ferroelectric hafnium zirconium oxide (HZO) for ferroelectric random-access memory (FeRAM). In recent years, ferroelectric materials have been extensively researched in the field of memory, with hafnium oxide-based ferroelectric materials emerging as promising candidates for next-generation memory applications due to their superior compatibility with array memory processes compared to traditional perovskite ferroelectric materials.
    This thesis is divided into three parts. The first part involves the development of memory devices with varying material thicknesses using equipment provided by the Taiwan Semiconductor Research Center and the National Yang Ming Chiao Tung University Nano Center. The second part focuses on the development of ferroelectric materials for array memory processes. The third part involves the modulation of different precursor deposition sequences using an atomic layer deposition (ALD) system to develop solid-solution (SS) and superlattice (SL) ferroelectric hafnium zirconium oxide (HfxZrxO2, HZO) stacking processes. The ferroelectric layer thickness is further reduced to achieve lower operating voltage, with the superlattice structure enhancing the crystallization of the ferroelectric oxide layer, advancing it’s application in memory arrays.

    1 第一章 緒論 1 1-1 FeRAM 用於陣列記憶體簡介 1 1-2 鐵電材料介紹 5 2 第二章 鐵電氧化鉿鋯記憶體製程材料開發 8 2-1 簡介 8 2-2 製程介紹 9 2-2-1 晶圓清洗 9 2-2-2 金屬沉積製程 10 2-2-3 原子氣相沉積 (ALD) 製程 12 2-2-4 曝光和顯影製程 13 2-2-5 蝕刻製程 16 2-2-6 高溫快速熱退火製程 18 2-3 結果討論 20 3 第三章 於記憶體陣列的鐵電氧化鉿鋯製程與分析 22 3-1 簡介 22 3-2 用於記憶體陣列中的鐵電氧化鉿鋯製程研究 23 3-2-1 去除晶圓水氣製程 23 3-2-2 鐵電氧化鉿鋯與電極金屬沉積 24 3-2-3 調變退火溫度分析 25 3-3 鐵電氧化鉿鋯電性分析 27 3-3-1 鐵電薄膜在 PUND測試中的特性 27 3-3-2 記憶體存取耐用性 (Endurance) 與保存性 (Retention) 測試 28 3-4 實驗結果 29 3-5 結論 30 4 第四章 低電壓操作減薄 SS-HZO和 SL-HZO製程與分析 32 4-1 簡介 32 4-2 減薄鐵電氧化鉿鋯製程 34 4-2-1 8 nm與6 nm Solid-Solution結構製程 34 4-2-2 8 nm與6 nm Superlattice結構製程 35 4-3 減薄鐵電氧化鉿鋯分析 36 4-3-1 低電壓操作 8 nm SS-HZO與 SL-HZO之 P-V量測 36 4-3-2 低電壓操作 6 nm SS-HZO與 SL-HZO之 P-V量測 37 4-3-3 低電壓操作2Pr值比較 39 4-4 實驗結果 40 4-5 結論 41 5 第五章 總結與未來展望 45 5-1 總結 45 5-2 未來展望 46 6 References 47 7 Publication 50

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