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| 研究生： |
洪嘉隆 Chia-Lung Hung |
|---|---|
| 論文名稱： |
高效能管線化架構之快速競爭式學習系統 An Efficient Pipelined Architecture for Fast Competitive Learning |
| 指導教授： |
黃文吉
Hwang, Wen-Jyi |
| 學位類別： |
碩士 Master |
| 系所名稱： |
資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年： | 2009 |
| 畢業學年度： | 97 |
| 語文別： | 中文 |
| 論文頁數： | 52 |
| 中文關鍵詞： | 可程式邏輯陣列 、競爭式學習 |
| 論文種類： | 學術論文 |
| 相關次數： | 點閱：131 下載：3 |
| 分享至: |
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中文摘要
本論文針對競爭式學習(competitive learning，CL)提出了一個全新的管線化(pipeline)架構，能夠有效的加速學習時間，此架構提出了神經元交換(swapping)的機制，來達到了不同訓練向量之間能夠同時進行神經元的競爭，有效增加神經元競爭階段時期的效能。而在神經元更新無可避免的除法部分，我們採用了查表式除法(lookup-table based division)，能夠在很低的面積複雜度之下依然擁有很高的精確度，同時有效的降低耗時的除法運算。
此架構以現場可程式邏輯陣列(field programmable gate array，FPGA)為實現平台，我們已測量出以Nios軟核心中央處理器執行此新管線化架構所需的CPU時間，而實驗結果顯示出了CPU時間遠遠低於未搭配硬體電路的Pentium IV處理器。
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