中文摘要
本論文針對競爭式學習(competitive learning，CL)提出了一個全新的管線化(pipeline)架構，能夠有效的加速學習時間，此架構提出了神經元交換(swapping)的機制，來達到了不同訓練向量之間能夠同時進行神經元的競爭，有效增加神經元競爭階段時期的效能。而在神經元更新無可避免的除法部分，我們採用了查表式除法(lookup-table based division)，能夠在很低的面積複雜度之下依然擁有很高的精確度，同時有效的降低耗時的除法運算。
此架構以現場可程式邏輯陣列(field programmable gate array，FPGA)為實現平台，我們已測量出以Nios軟核心中央處理器執行此新管線化架構所需的CPU時間，而實驗結果顯示出了CPU時間遠遠低於未搭配硬體電路的Pentium IV處理器。

參考文獻
[1] Altera Corporation (2005). Stratix Device Handbook. http://www.altera.com/literature/lit-stx.jsp.
[2] Altera Corporation (2002). Custom Instructions for NIOS Embedded Processors,
Application Notes 188. http://www.altera.com/literature/lit-nio.jsp.
[3] NIOS II Processor Reference Handbook, 2008, Altera Corporation. http://www.altera.com/literature/lit-nio2.jsp.
[4] Bei, C. D.; Gray, R.M. An Improvement of the Minimum Distortion Encoding Algorithm for Vector Quantization, IEEE Trans. Communication 1985, Vol. COM-33, pp.1132-1133..
[5] Bondalapati, K.; Prasanna, V.K. Reconfigurable computing systems, Proceedings of the IEEE, pp.1201-1217, 2002.
[6] Colavita, A. A.; Cicuttin, A.; Fratnik, F.; Capello, G. SORTCHIP: A VLSI Implementation of a Hardware Algorithm for Continuous Data Sorting, IEEE Journal of Solid-State Circuits 2003, Vol. 38, pp 1076-1079.
[7] Cole, R.; Seigel, A. R. Optimal VLSI circuit for sorting, Journal of ACM 1998, Vol. 35, pp. 777-809.
[8] Gersho, A.; Gray, R.M. Vector Quantization and Signal Compression, Kluwer: Norwood, MA, 1992.
[9] Grossberg, S. Competitive Learning: From Interactive Activation to Adaptive Response, Cognitive Science 1987, Vol. 11, pp.23-63.
[10] Hauck, S., and Dehon, A., Reconfigurable Computing, Morgan Kaufmann, 2008.
[11] Haykin, S. Neural Networks: A Comprehensive Foundation, Prentice Hall: Engle Cliffs, NJ, 1998.
[12] Hertz, J.; Krogh, A.; Palmer, R.G. Introduction to the Theory of Neural Computation, Addison-Wesley: New York, NY, 1991.
[13] Hwang, W. J.; Lin, F.J.; Zeng, Y.C. Fast Design Algorithm for Competitive Learning, Electronics Letters 1997, Vol.33, pp.1469-1470.
[14] Hwang, W. J.; Ye, B. Y.; Lin, C. T. A Novel Competitive Learning Algorithm for the Parametric Classification with Gaussian Distributions, Pattern Recognition Letters 2000, Vol.21, pp.375-380.
[15] Hofmann, T.; Buhmann, J.M. Competitive Learning Algorithm for Robust Vector Quantization, IEEE Trans. Signal Processing 1998, Vol. 46, pp. 1665-1675.
[16] Jain, A.K., Murty, M.N., and Flynn, P.J.,Data Clustering: A Review, ACM Computing Surveys, 1999, pp. 264-323.
[17] Kohonen, T. The self-organizing map, Proc. IEEE 1990, Vol. 78, pp.1464-1480.
[18] Li, H.Y.; Hwang, W.J.; Yang, C.T. High Speed k-Winner-Take-ALL Competitive Learning in Reconfigurable Hardware, Lecture Notes in Artificial Intelligence, IEA-AIE 2009.
[19] Park, H.; Prasanna, V. K. Modular VLSI architectures for Real-Time Full-Search-Based Vector Quantization, IEEE Trans. Circuits Syst. Video Technology 1993, Vol.3, pp.309-317.
[20] Vetterli, M.; Kovacevic, J. Wavelets and Subband Coding, Prentice Hall: Engle Cliffs, NJ, 1995.
[21] Wang, C.L.; Chen, L.M. A New VLSI Architecture for Full-Search Vector Quantization, IEEE Trans. Circuits and Systems for Video Technology 1996,Vol. 6, pp.389-398.
[22] Wolfe, W. J.; Mathis, D.; Anderson, C.; Rothman, J.; Gottler, M.; Brady, G.; Walker, R.; Duane, G. K-Winner Networks, IEEE Trans. Neural Networks 1991, Vol. 2, pp.310-315.

[23] Xu, L.; Krzyzak, A.; Oja, A. E. Rival penalized competitive learning for clustering analysis, RBFnet, and curve detection, IEEE Trans. Neural Networks 1993, Vol. 4, pp.636-649.