本論文主要針對77 GHz汽車防撞雷達微波CMOS射頻前端RFICs以及毫米波電路設計研究討論，晶片製作透過國家晶片中心提供的標準TSMC CMOS 90nm製程，內容分為兩個部分，第一個部分為介紹毫米波汽車防撞雷達研究背景，第二部分為毫米波CMOS RFICs之設計與量測。
論文將介紹三個電路，第一個為低雜訊放大器，此設計頻率為71至77 GHz設計上採用三級串接，第一級為共源級組態，主要考量於低雜訊之訴求，第二級與第三級將採用疊接組態，疊接組態將提供高增益，來滿足系統所需之規格，本設計考量將在疊接組態之增益以及雜訊指數，利用中間匹配電感來設計，其電感可以使疊接組態之雜訊指數降低，並可以提高增益，本論文於第三章內容將作設計考量分析，而量測結果在74 GHz時有最小雜訊指數 6.17 dB，增益高達20 dB以上，晶片面積為0.596 ╳ 0.583 mm2。第二個電路為功率放大器，此設計操作頻率為71至77 GHz，設計考量於功率為重，因此在架構上選擇較大之電晶體，且採用疊接組態提高增益，量測結果於頻率71至77 GHz增益維持在20 dB，其晶片面積大小為0.596 ╳ 0.596mm2。第三部分為混頻器，採用環型混頻器架構，系統主要於低LO功率，以及低功率消耗，供應電壓為1.2 V，操作頻率在71至77 GHz，降頻混頻器之OP1dB發生在輸入RF功率為-3 dBm時有-0.5 dBm輸出功率。

The subject is design of 77 GHz millimeter-wave integrated circuits for
Anticollison radar applications. The presented low noise amplifier, power amplifier, down/up-conversion ring mixers are designed and fabricated on TSMC 90 nm 1P9M CMOS process. The Contents divide into two parts. The first part is the background of Millimeter-wave auticollision radar. The second part is simulation and measurement data.
The paper presents three circuits. One is low noise amplifier. The LNA utilizes three-stage configuration amplifier. The first stage is common source due to small low noise figure. The second and third stages are cascade because of the high gain. The low noise amplifier is simulated at 71-77 GHz. Noise figure is 6.17 dB at frequency 74 GHz. The gain is 20 dB. The chip size is 0.596 ╳ 0.583 mm2. The second is power amplifier . the amplifier utilizes three-stage configuration and large size transistors to design. the result of gain measurement is 20 dB. The chip size is 0.596 ╳ 0.596 mm2. the final part is down/up-conversion ring mixers. The OP1dB of down-conversion mixer is -0.5 dBm @ -3 dBm.

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