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研究生: 蕭璿
Hsiao, Hsuan
論文名稱: 應用於毫米波相位陣列系統之相移器設計
Design of Phase Shifters for Millimeter Wave Phase Array System
指導教授: 蔡政翰
Tsai, Jen-Han
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 中文
論文頁數: 229
中文關鍵詞: Ka頻段毫米波物聯網第五代行動通訊向量合成式相移器開關式相移器反射式相移器相位陣列相位可反相衰減器
英文關鍵詞: millimeter wave, vectorsum phases shifter, reflection type phaseshifter, phase array
DOI URL: http://doi.org/10.6345/THE.NTNU.DEE.002.2019.E08
論文種類: 學術論文
相關次數: 點閱:215下載:14
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  • 近年來隨著物聯網(Internet of Things, IOT)與第五代行動通訊(5th Generation Mobile Networks, 5G)帶動高速通訊的發展,資料傳輸需要更寬的頻寬來滿足大量傳輸需求,傳輸頻段必須往更高頻段移動,因此高頻訊號先天路徑損耗較大的問題變成必須克服的難題,本論文主要研究毫米波相位陣列系統之相移器設計,利用波束成形(Beamforming)技術來解決高頻傳輸路徑損耗過大問題。
    第三章介紹ka頻帶五位元開關式相移器,電路採用電路採用標準0.18-μm 1P6M互補式金屬氧化物半導體製程(Standard 0.18-μm 1P6M CMOS process)實現,其中四個位元採用T橋式相移器架構,另一位元採用高低通網路架構。電路功率消耗為0mW,整體晶片面積為0.84 mm2,操作頻率為26GHz至31GHz,輸入反射係數小於-7.1dB、輸出反射係數小於-5.2dB、RMS相位誤差小於5.37°、RMS振幅誤差小於0.85dB。
    第四章為了改善第三章相移頻寬,將90°相移器採用反射式架構,180°相移器採用相位可反相衰減器,其餘位元皆採用T橋式相移器架構。操作頻率為26至31GHz,電路功率消耗為0 mW,整體晶片面積0.64 mm2,輸入反射係數小於-13.4dB,輸出反射係數小於-5.5dB,RMS相位誤差小於3.07°,RMS振幅誤差小於1.06dB。
    第五章介紹ka頻帶五位元開關式相移器,電路採用標準65-nm 1P9M互補式金屬氧化物半導體製程(Standard 65-nm 1P9M CMOS process)實現,為了降低相移器之間的負載效應,將180°相移器採用兩個90°T橋式相移器組成,使得五位元相移器皆採用T橋式相移器架構。電路功率消耗為0 mW,整體晶片面積為0.39mm2,操作頻率為36GHz至40GHz,輸入反射係數小於-8.8dB、輸出反射係數小於-8.2 dB、RMS相位誤差小於7.3°、RMS振幅誤差小於1.8 dB。
    第六章介紹ka頻帶向量合成式相移器,相移解析度為5Bit,控制電路電壓解析度為6Bit,電路採用標準65-nm 1P9M互補式金屬氧化物半導體製程(Standard 65-nm 1P9M CMOS process)實現,電路功率消耗為6.6mW,整體晶片面積為0.37mm2,操作頻率為36GHz至40GHz,輸入反射係數小於-19.6dB,輸出反射係數小於-5.5dB,RMS振福誤差小於0.17dB,RMS相位誤差小於1.67°。

    In recent years, with the development of high-speed communication between the Internet of Things and the fifth-generation mobile communication, data transmission requires a wider bandwidth to meet a large number of data transmission, transmission frequency must move to a higher frequency to obtain high frequency bandwidth requirements. Therefore, the problem of high frequency signal intrinsic path loss becomes a problem that must be overcome. This paper studies the phase shifter design of millimeter wave phase array system, using beamforming. Technology to solve the problem of excessive loss of high frequency transmission path.
    Chapter3 introduces the ka-band five-bit switching phase shifter. The circuit is implemented by standard 0.18-μm 1P6M complementary metal oxide semiconductor process (Standard 0.18-μm 1P6M CMOS process), in which four bits adopt T-bridge. The phase shifter architecture uses another high-low-pass network architecture. The circuit power consumption is 0mW, the overall chip area is 0.84 mm2, the operating frequency is 26GHz to 31GHz, the input reflection coefficient is less than -7.1dB, the output reflection coefficient is less than -5.2dB, the RMS phase error is less than 5.37°, and the RMS amplitude error is less than 0.85dB
    Chapter4 improve the problem of poor phase shift bandwidth in Chapter 3, the 90° phase shifter adopts Reflection Type Pahse Shifter (RTPS) and the 180° phase shifter uses phase Invertible Variable Attenuator(PIVA), the remaining bits are all T-bridge architecture. The operating frequency is 26 to 31 GHz, the circuit power consumption is 0 mW, the overall wafer area is 0.64 mm2, the input reflection coefficient is less than -13.1 dB, the output reflection coefficient is less than -5.5 dB, the RMS phase error is less than 3.07 °, and the RMS amplitude error is less than 1.06 dB.
    Chapter5 introduces the ka-band five-bit switching phase shifter. The circuit is implemented by standard 65-nm 1P9M complementary metal oxide semiconductor process (Standard 65-nm 1P9M CMOS process), in order to reduce the load effect between phase shifters. The 180° phase shifter is composed of two 90° T bridge phase shifters, so that the five-bit phase shifter adopts the T-bridge phase shifter architecture. The circuit power consumption is 0 mW, the overall chip area is 0.39mm2, the operating frequency is 36GHz to 40GHz, the input reflection coefficient is less than -8.8dB, the output reflection coefficient is less than -8.2dB, the RMS phase error is less than 7.3°, and the RMS amplitude error is less than 1.8 dB.
    Chapter6 introduces the Ka-band vector synthesis phase shifter. The circuit is implemented by the standard 65-nm 1P9M complementary metal oxide semiconductor process (Standard 65-nm 1P9M CMOS process), the phase shift resolution is 5Bit, and the control circuit is adjustable. With a resolution of 6Bit, this architecture provides an adjustable continuous phase. In practice, a 6Bit Digital Analog Converter (DAC) must be integrated. The circuit power consumption is 6.6mW, the overall chip area is 0.37mm2, the input reflection coefficient is less than -19.6dB, the output reflection coefficient is less than -5.5dB, the RMS vibration error is 0.17dB, and the RMS phase error is 1.67°

    摘要 i ABSTRACT iii 致謝 vi 目錄 vii 圖目錄 xi 表目錄 xxiii 第一章 緒論 1 1.1 研究背景與動機 1 1.2 文獻探討 2 1.2.1 相移器文獻探討 2 1.3 研究成果 6 第二章 相移器介紹 7 2.1 簡介 7 2.2 相移器參數介紹 7 2.2.1 相位差 (Phase Difference) 7 2.2.2 插入損耗、振幅誤差 (Insertion Loss, Amp. Error) 7 2.2.3 RMS 相位差 (RMS Phase Error) 8 2.2.4 RMS振幅誤差 (RMS Amplitude Error) 8 2.2.5 1dB增益壓縮點 ("P1dB" ) 8 2.2.6 反射係數 (Return Loss) 9 2.3 相移器電路介紹 9 2.3.1 傳輸線式相移器 9 2.3.2 開關式相移器 11 2.3.3 反射式相移器 16 2.3.4 向量和式相移器 17 第三章 Ka頻帶五位元開關式相移器設計 19 3.1 簡介 19 3.2 Ka頻帶五位元開關式相移器設計 20 3.2.1 電路架構 20 3.2.2 理想相移器電容、電感模擬 20 3.2.3 電晶體尺寸設計 27 3.2.4 各主要位元相移器單獨Post-sim模擬 36 3.3 角度補償過程 43 3.3.1 五位元相移器模擬 45 3.3.2 五位元相移器量測 50 3.3.3 五位元相移器加入反相器佈局量測 58 3.4 問題與討論 66 3.4.1 量測方式探討 66 3.5 總結 66 第四章 Ka頻帶180°相位可反相衰減器與90°反射式相移器 69 4.1 簡介 69 4.2 電路架構 69 4.2.1 反射式相移器與相位可反相衰減器相移器介紹 70 4.2.2 正交耦合器設計 71 4.2.3 180°相位可反相衰減器反射負載設計 72 4.2.4 90°反射負載反射負載設計 76 4.2.5 五位元相移器模擬 80 4.2.6 五位元相移器量測 85 4.3 第二次下線角度補償修正模擬 92 4.3.1五位元相移器修正模擬量測 97 4.4 問題與討論 104 4.4.1 反射式相移器與T橋式相移器模擬比較 105 4.4.2 反射負載敏感度測試 109 4.5 總結 111 第五章 65nm CMOS Ka頻帶五位元開關式相移器設計 113 5.1 電路設計流程 113 5.2 五位元開關式相移器電路設計 114 5.2.1 電路架構 114 5.2.2 T橋式相移器理想LC相移模擬 114 5.2.3 電晶體尺寸設計 121 5.2.4 各主要位元相移器Post-sim模擬 127 5.3 位元開關式相移器相移模擬 133 5.4 五位元開關式相移器相移器量測 141 5.5 電路除錯 148 5.6 第二次下線相移器角度補償設計 153 5.6.1 五位元開關式相移器第二次下線模擬 154 5.6.2 五位元開關式相移器第二次下線量測 158 5.7 問題與討論 166 5.7.1 位元順序與振幅誤差探討 166 5.7.2 高低通網路與兩個T橋式90°比較 174 5.8總結 178 第六章 向量合成式相移器設計 181 6.1 簡介 181 6.2 相量合成式相移器電路設計 182 6.2.1 電路架構 182 6.3 被動部分電路設計 182 6.3.1 正交耦合器設計 183 6.3.2 Marchand Balun 設計 185 6.3.3 正交相位產生器設計 187 6.4 主動電路部分設計 188 6.4.1 電晶體尺寸設計 189 6.5 向量合成式相移器模擬 191 6.6 向量合成式相移器量測 198 6.7 問題與討論 205 6.7.1 修改控制電路的電壓方式改善振幅誤差 205 6.7.2 修改控制電路的電壓方式重新量測晶片 214 6.8 總結 220 第七章 結論 223 參考文獻 225 自 傳 229 學術成就 229

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