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研究生: 馬瑜傑
Yu-chieh Ma
論文名稱: 應用於極座標發射機封包調變之延遲鎖定迴路建構脈波寬度調變器設計與實現
Design and Implementation of DLL-based PWM for Envelope Modulation of Polar Transmitters
指導教授: 郭建宏
Kuo, Chien-Hung
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 96
中文關鍵詞: 脈波寬度調變器多相位延遲鎖定迴路極座標發射機封包調變長期演進技術
英文關鍵詞: Pulse-Width Modulation, Multi-phase Delay-Locked Loop, Polar-Transmitter, Envelope Modulation, Long Term Evolution
論文種類: 學術論文
相關次數: 點閱:211下載:12
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  • 近年來極座標發射機有關的文獻中,脈波寬度調變器(Pulse-Width Modulator, PWM)和三角積分調變器(Delta-Sigma Modulator, DSM),皆有被提出使用在發射機前端的封包調變[1]-[4]。對於需要高解析和高線性調變器的寬頻通訊系統而言,DSM就必須提高其量化器的位元數,才能通過寬頻通訊規格,但整體發射機需要的功率放大器個數就會倍增。幸運的是,若提高PWM的操作頻率,其所造成的諧波雜訊可輕易的被後端帶通濾波器濾除,所需的功率放大器也可少於DSM。

    本論文提出一個應用於封包調變之延遲鎖定迴路建構脈波寬度調變器。為了達到高解析高線性的需求,一個128個相位輸出的延遲鎖定迴路被用來組合出64種置中型脈波寬度變化。本論文提出一個循環式壓控延遲線來減少延遲元件的個數,使得所有的128個相位可以同時地輸出。藉由一個簡易計數器,我們可將所有相位分為上升區以及下降區,來產生所需的脈波寬度輸出。本論文提出之延遲鎖定迴路建構脈波寬度調變器使用台積電90奈米製程。其整體功率消耗為36.83 mW,操作頻率為92.16MHz,供應電壓為1.2V。

    In recent years, the pulse-width modulation (PWM) and delta-sigma modulation (DSM) are two popular approaches used for the front-end of the envelope modulator in traditional polar transmitters[1]-[4]. For the wide bandwidth modern communications, a high resolution and high linearity of modulator is needed. So, the DSM must increase the bits of quantizer to meet the specification, but it would make the design of post-PAs difficult to be realized. Fortunately, if the operational frequency of PWM could be appropriately increased, the annoying harmonic effect would be easily attenuated by the post-bandpass filter and the number of the post-PAs is less than DSM.

    This thesis presents a DLL-based PWM for the envelope modulation of polar transmitters. For the requirements of high resolution and high linearity, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a cyclic voltage controlled delay line is presented in this thesis. The 128 output phases can be simultaneously produced by the 8-delay units of VCDL. A simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed DLL-based PWM is fabricated by TSMC 90nm 1P9M process. The power consumption is 36.83 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.

    摘  要 i ABSTRACT iii 致  謝 v 目  錄 vii 表 目 錄 x 圖 目 錄 xi 第一章 緒論 1 1.1 研究背景 1 1.2  研究目的 7 1.3  論文組成 8 第二章 應用於封包調變的脈波寬度調變器 9 2.1 極座標發射機介紹 9 2.2 極座標發射機封包調變中的脈波寬度調變器需求 10 2.3 系統所需規格之評估 18 第三章 延遲鎖定迴路設計 20 3.1 典型的延遲鎖定迴路 20 3.2 延遲鎖定迴路基本子電路介紹 21 3.2.1 相位頻率偵測器 21 3.2.2 電荷幫浦與迴路濾波器 24 3.2.3 壓控延遲線 25 3.2.3.1 RC時間常數之延遲元件 26 3.2.3.2 可變電容式之延遲元件 26 3.2.3.3 餓電流(Current-starved)控制之延遲元件 27 3.2.3.4 差動對稱性負載之延遲元件 27 3.3 鎖定範圍 28 3.3.1 諧波鎖定 29 3.3.2 阻塞鎖定 30 3.4 系統穩定性分析 31 3.5 多相位延遲鎖定迴路 35 第四章  延遲鎖定迴路建構脈波寬度調變器 40 4.1 使用循環式壓控延遲線之多相位延遲鎖定迴路 40 4.1.1 電路描述 42 4.1.1.1 循環式壓控延遲線的脈衝輸入限制 42 4.1.1.2 延遲元件 44 4.1.1.3 相位頻率偵測器 47 4.1.1.4 電荷幫浦 48 4.1.1.5 鎖定偵測器 49 4.1.1.6 可程式電壓控制器 49 4.1.1.7 開關控制以及脈衝產生器 51 4.2 脈波寬度調變迴路 52 4.2.1 電路描述 53 4.2.1.1 八對一多工器 53 4.2.1.2 三位元上下數計數器 54 4.2.1.3 數位比較器 55 4.2.1.4 相位合成器 56 4.3 靜電放電防護設計(Electrostatic Discharge, ESD) 56 4.3.1 電路描述 57 4.3.1.1 二極體防護電路 57 4.2.1.2 電源箝制電路 58 4.4 模擬結果和晶片佈局圖 60 第五章 延遲鎖定迴路建構脈波寬度調變器之量測 71 5.1 元件前置準備 71 5.2 測試板之設計 74 5.3 使用儀器 76 5.4 量測環境與結果 77 第六章 結論與未來展望 87 6.1 結論與未來展望 87 6.2 文獻比較 88 參 考 文 獻 90 自  傳 95 學 術 成 就 96

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