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研究生: 林佳龍
Lin, Chia-Lung
論文名稱: 5.3 GHz互補式金屬氧化物半導體功率放大器與線性化技術研究
Research on 5.3 GHz CMOS Power Amplifiers and Linearization Technique
指導教授: 蔡政翰
Tsai, Jen-Han
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 中文
論文頁數: 135
中文關鍵詞: 互補式金屬氧化物半導體功率放大器線性器變壓器功率合成技術無線區域網路5.3 GHz
英文關鍵詞: CMOS, power amplifiers, linearizer, transformer, power combining techniques, WLAN, 5.3-GHz
DOI URL: https://doi.org/10.6345/NTNU202203077
論文種類: 學術論文
相關次數: 點閱:146下載:4
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  • 本論文研製之三個5.3 GHz功率放大器分別利用變壓器功率合成技術、電流合成變壓器技術與內建線性器技術來設計,並實現於標準0.18-μm 1P6M互補式金屬氧化物半導體製程(Standard 0.18-μm 1P6M CMOS process)中。本論文之功率放大器量測包含了S參數與連續波訊號。
    第一個電路為利用變壓器功率合成技術之5.3 GHz功率放大器,透過變壓器的阻抗轉換與功率結合之能力,達成輸入共軛匹配、輸出功率阻抗匹配與高輸出功率。當功率放大器的Vg1為0.85 V時,其功率增益(Power gain)約為18.19 dB,飽和輸出功率Psat約為26.10 dBm,1-dB增益壓縮點之輸出功率OP1dB約為21.20 dBm,靜態電流約為294.60 mA,最大功率附加效率Peak PAE約為21.30 %,整體晶片佈局面積為1.17 mm × 0.64 mm。
    第二個電路為利用電流合成變壓器技術之5.3 GHz功率放大器,以第一個電路為基礎,為了得到更高的輸出功率,我們透過電流合成變壓器技術將其輸出端做功率結合,並達到輸出功率提升近3 dBm的效果。當功率放大器的Vg1為0.85 V時,其功率增益(Power gain)約為16.43 dB,飽和輸出功率Psat分別約為29.43 dBm,1-dB增益壓縮點之輸出功率OP1dB約為25.44 dBm,靜態電流約為610.50 mA,最大功率附加效率Peak PAE約為23.06 %,整體晶片佈局面積為1.09 mm × 1.16 mm。
    第三個電路為具內建線性器之5.3 GHz功率放大器,以第二個電路為基礎,在其輸入端掛接一疊接組態線性器,並透過改變線性器之控制電壓Vctrl而達到控制功率放大器之線性度改善的程度。當功率放大器的Vg1為0.85 V且線性器開啟時,功率增益約14.04 dB,飽和輸出功率Psat約為28.66 dBm,1-dB增益壓縮點之輸出功率OP1dB約為25.11 dBm,最大功率附加效率Peak PAE約為21.00 %,三階交互調變失真IMD3在輸出功率約為19.45 dBm以前皆可抑制在-40 dBc左右,整體晶片佈局面積為1.09 mm × 1.16 mm。

    In this paper, three 5.3-GHz power amplifiers are presented, which were separately utilized the technique of transformer power combining, current combining transformer and built-in linearizer, and implemented in TSMC standard 0.18-μm 1P6M CMOS technology. The measurements of three power amplifiers include s-parameters and continuous wave signal.
    First, a 5.3 GHz power amplifier with transformer power combining technique has been designed and implemented. To achieve input impedance matching, output power matching and high output power, we utilize the transformer to implement the impedance conversion and the power combining. When the Vg1 of the power amplifier operating in 0.85 V, the power amplifier exhibits the power gain of 18.19 dB, the saturated output power of 26.10 dBm, the output power of 21.20 dBm at 1-dB compression point, the quiescent current of 294.60 mA and the maximum power added efficiency of 21.30 %. The chip size is 1.17 mm × 0.64 mm.
    Second, based on the first circuit, a 5.3 GHz power amplifier with current combining transformer technique has been designed and implemented. To achieve the higher output power, current combining transformer technique is adopted. When the Vg1 of the power amplifier operating in 0.85 V, the power amplifier demonstrates the power gain of 16.43 dB, the saturated output power of 29.43 dBm, the output power of 25.44 dBm at 1-dB compression point, the quiescent current of 610.50 mA and the maximum power added efficiency of 23.06 %. The chip size is 1.09 mm × 1.16 mm.
    Finally, based on the second circuit, a built-in linearizer utilizing cascode configuration for 5.3 GHz power amplifier has been designed and implemented. The proposed linearization technique which is shunted in the front end of the second circuit aims to control the implement of the linearity of the power amplifier by the Vctrl. After linearization with the Vg1 of the power amplifier operating at 0.85 V, the power amplifier demonstrates the power gain of 14.04 dB, the saturated output power of 28.66 dBm, the output power of 25.11 dBm at 1-dB compression point and the maximum power added efficiency of 21.00 %. Third-order intermodulation distortion can be suppressed below to -40 dBc until the output power of 19.45 dBm. The chip size is 1.09 mm × 1.16 mm.

    摘 要 I ABSTRACT III 誌 謝 V 目 錄 VII 圖目錄 XI 表目錄 XVII 第一章 緒論 1 1.1 研究背景與動機 1 1.2 文獻探討 3 1.3 研究成果 5 1.4 論文架構 6 第二章 功率放大器基本介紹 7 2.1 概述 7 2.2 功率放大器之設計參數 [12]-[15] 8 2.2.1 散射參數(S-parameters) 8 2.2.2 功率(Power) 9 2.2.3 效率(Efficiency) 9 2.2.4 線性度(Linearity) 10 2.3 功率放大器種類 13 第三章 利用變壓器功率合成技術之5.3 GHz功率放大器設計 15 3.1 簡介 15 3.2 利用變壓器功率合成技術之5.3 GHz功率放大器設計 17 3.2.1 偏壓分析與選擇 17 3.2.2 電晶體元件尺寸分析與選擇 19 3.2.3 功率放大器組態選擇 21 3.2.4 變壓器原理 26 3.2.5 變壓器分析 27 3.2.6 變壓器設計 30 3.2.7 旁路電路設計 46 3.3 功率放大器之模擬結果 50 3.4 功率放大器之量測結果 56 3.5 結果與討論 64 3.6 總結 69 第四章 利用電流合成變壓器技術之5.3 GHz功率放大器設計 71 4.1 簡介 71 4.2 利用電流合成變壓器技術之5.3 GHz功率放大器設計 72 4.2.1 電流合成變壓器技術簡介 72 4.2.2 電流合成變壓器設計 73 4.3 功率放大器之模擬結果 83 4.4 功率放大器之量測結果 89 4.5 結果與討論 96 4.6 總結 97 第五章 具前置預失真線性器之5.3 GHz功率放大器設計 99 5.1 簡介 99 5.2 具前置預失真線性器之5.3 GHz功率放大器設計 100 5.2.1 線性器原理簡介 100 5.2.2 具內建線性器功率放大器之增益分析 102 5.2.3 線性器架構選擇 103 5.2.4 線性器尺寸分析與選擇 105 5.3 具前置預失真線性器之功率放大器模擬結果 106 5.4 功率放大器之量測結果 112 5.5 結果與討論 120 5.6 總結 126 第六章 結論 129 參考文獻 131 自傳 135 學術成就 135

    [1] National Instrument WLAN應用說明: Introduction to Wireless LAN Measurements From 802.11a to 802.11ac
    [2] Tektronix datasheet: Tektronix wifi solutions 802.11 datasheet,2013
    [3] National Instrument技術文件: Introduction to 802.11ax High-Efficiency Wireless,http://www.ni.com/white-paper/53150/en/,2016
    [4] 2016是德科技電子量測論壇: A-2 Overview of Latest WiFi Technologies and Test Solution,2016
    [5] P. Haldi, D. Chowdhury, and P. Reynaert, “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1054-1063, May 2008.
    [6] C. S. Wu, C. H. Chang, H. C. Liu, T. Y. Ko, and H. C. Chiu, “High Linearity 5.3 GHz Power Amplifier MMIC using the Linearizer Circuit”, Microwave Conference 2008 China-Japan Joint, pp. 633-635, Sep. 2008.
    [7] D. Gruner, and G. Boeck, “Fully integrated 5.6-6.4 GHz power amplifier using transformer combining,” Conferene on Ph. D. Research in Microelectronics and Electronics PRIME, 2009.
    [8] T.-P. Wang, J.-H. Ke, and C.-Y. Chiang, “A high-Psat high-PAE ful-ly-integrated 5.8-GHz power amplifier in 0.18-µm CMOS,” in IEEE Electron Devices and Solid-State Circuits (EDSSC), pp. 1-2, Nov. 2011.
    [9] C.-C. Kuo, Y.-W. Hsu, W.-C. Huang, H. Wang, and H.-C. Lu, “Performance Comparison of Flip-Chip-Assembled 5-GHz 0.18-μm CMOS Power Amplifiers on Different Packaging Substrates,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 3, no. 12, pp. 2014-2021, Dec. 2013.
    [10] J.-H. Tsai, and H.-W. Ou-Yang, “A 5-5.8 GHz Fully-Integrated CMOS PA for WLAN Applications,” 2014 IEEE Radio and Wireless Symposium (RWS), pp. 130 – 132, Jan. 2014.
    [11] B. François, and P. Reynaert, “A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 50, no. 5, pp. 1237-1250, May 2015.
    [12] G. Gonzalez, Microwave Transistor Amplifier Analysis and Design, 2nd ed., Prentice Hall, 1997.
    [13] B. Razavi, RF Microelectronics, 2nd ed., Prentice Hall, 2012.
    [14] S. C. Cripps, RF POWER AMPLIFIERS FOR WIRELESS COMMUNICATIONS, 2nd ed., Artech House, 2006.
    [15] D. M. Pozar, Microwave Engineering, 3rd ed., John Wiley & Sons Inc., 2004.
    [16] J. Kim, Y. Yoon, H. Kim, K. H. An, W. Kim, H.-W. Kim, C.-H. Lee, and K. T. Kornegay, “A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1034-1048, May 2011.
    [17] Y. Wang, and J.-S. Yuan, “An Integrated CMOS High Power Amplifier using Power Combining Technique,” 2012 Proceedings of IEEE, pp. 1-6, Mar 2012.
    [18] J. Kim, W. Kim, H. Jeon, Y.-Y. Huang, Y. Yoon, H. Kim, C.-H. Lee, and K. T. Kornegay, “A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 599-614, Mar. 2012.
    [19] J. Oh, B. Ku, and S. Hong, “A 77-GHz CMOS Power Amplifier With a Parallel Power Combiner Based on Transmission-Line Transformer,” IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 7, pp. 2662-2669, July 2013.
    [20] C.-C. Kuo, Y.-H. Lin, H.-C. Lu, and H. Wangand, “A K-band Compact Fully Integrated Transformer Power Amplifier in 0.18-μm CMOS,” 2013 Asia-Pacific Microwave Conference Proceedings (APMC), pp. 597-599, Nov. 2013.
    [21] J.-F. Yeh, Y.-F. Hsiao, J.-H. Tsai, T.-W. Huang, “MMW Ultra-Compact -Way Transformer PAs Using Bowtie-Radial Architecture in 65-nm CMOS,” IEEE Microwave and Wireless Components Letters, vol. 25, no. 7, pp. 460-462, July 2015.
    [22] B. Leite, E. Kerhervé, and D. Belot, “Design of 28 nm CMOS integrated transformers for a 60 GHz power amplifier,” 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1-6, Aug 2015.
    [23] J.-H. Cheng, S.-J. Luo, W.-J. Lin, J.-H. Tsai, and T.-W. Huang, “A 24-GHz Transformer-Based Stacked-FET Power Amplifier in 90-nm CMOS Technology,” 2015 Asia-Pacific Microwave Conference (APMC), vol. 3, pp. 1-3, Dec. 2015.
    [24] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Distributed Active Transformer—A New Power-Combining and Impedance-Transformation Technique,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, pp. 316-331, Jan. 2002.
    [25] Y. Han, and D. J. Perreault, “Analysis and Design of High Efficiency Matching Networks,” IEEE Transactions on Power Electronics, vol. 21, no. 5, pp. 1484-1491, Sept. 2006.
    [26] A.M. Niknejad, electromagnetics for high-speed analog and digital communication circuits, Cambridge University Press, Mar. 2007.
    [27] A. M. Niknejad, D. Chowdhury, and J. Chen, “Design of CMOS Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 6, pp. 1784-1796, Jun. 2012.
    [28] V. Freitas, J.-D. Arnould, and P. Ferrari, “General Expression for Tunable Matching Network Efficiency in the case of complex impedances,” Microwave & Optoelectronics Conference (IMOC), pp. 1-5, Aug. 2013.
    [29] J.-H. Tsai, H.-Y. Chang, P.-S. Wu, Y.-L. Lee, T.-W. Huang, and H. Wang, “Design and Analysis of a 44-GHz MMIC Low-Loss Built-In Linearizer for High-Linearity Medium Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 6, pp. 2487-2496, Jun. 2006.
    [30] K.-Y. Kao, Y.-C. Hsu, K.-W. Chen, and K.-Y. Lin, “Phase-Delay Cold-FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 12, pp. 4505-4519, Dec. 2013.
    [31] J.-F. Yeh, J.-H. Cheng, J.-H. Tsai, and T.-W. Huang, “A 57-66 GHz power amplifier with a linearization technique in 65-nm CMOS technology,” Microwave Conference (EuMC), pp. 1253-1256, Oct. 2014.
    [32] T.-Y. Huang, Y.-H. Lin, and H. Wang, “A K-Band Adaptive-Bias Power Amplifier with Enhanced Linearizer Using 0.18-um CMOS Process,” 2015 IEEE MTT-S International Microwave Symposium, pp. 1-3, May. 2015.

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