超級電容(Supercapacitors)擁有快速充放電、功率密度高、元件壽命長等優點，可應用於行動通訊、車輛運輸、智慧電網等領域。然而，目前超級電容的製作技術中，許多是利用平面金屬電極，再加上碳海綿、碳氣凝膠或電紡絲碳纖維等3D多孔碳結構，意圖以增加碳活性材料之比表面積的方式，達到提高電容器功率密度之目的。然而，這些平面金屬加上3D多孔碳結構的電極，當元件受到大應力、高速撞擊與震動的作用下，這種平面金屬/多孔碳結構將產生嚴重的的脫層或塌陷而失效，使其無法應用於國防工業、航天太空、電動載具等抗壓耐震需求之超級電容上。
因此，本研究將使用三種製程方式製作矽基電極，第一種製程只使用光輔助電化學蝕刻（Photo-assisted electrochemical etching, PAECE）製程，在參數為氫氟酸10 wt% 界面活性劑酒精1 wt%、偏壓為3.5 V、蝕刻時間為8 hr的情況下，可以得到深度約為222 μm的隨機矽孔洞結構；第二種製程為使用黃光製程與反應性離子蝕刻技術，事先定義出陣列圖案的蝕刻窗後，再以光輔助電化學蝕刻技術製作，在參數為氫氟酸2.5 wt%、界面活性劑 DC 1 wt%、偏壓3 V、蝕刻時間 2 hr之下完成深度約為162 μm之矽孔洞結構；第三種製程為先使用ICP-RIE技術製作巨孔洞陣列結構，再以光輔助電化學蝕刻技術粗化孔洞結構內壁，參數為氫氟酸2.5 wt%、界面活性劑 DC 5 wt%、偏壓1 V、蝕刻時間 2 hr。三種多孔矽結構完成後，分別使用化學氣相沉積(Chemical vapor deposition)在其表面生成碳膜，此可鈍化多孔矽表面電荷陷阱(Surface charge traps)並增加導電性，再將混拌石墨烯薄片(graphene)、二氧化釕(RuO2)、高分子材料(PVA)的酸性電解液，以真空抽氣方式滲入多孔結構中並固化，以實現高抗壓耐震性超級電容之開發，後續再利用恆電位儀進行C-V特性曲線(C-V curve)量測、恆電流充放電曲線(Galvanostatic charge/discharge curve)等量測分析。由於使用第二種製備法之矽基電極在量產結構時遇到稜線蝕刻過度的問題，而不適用於超級電容之製作，第三組製程則是在組裝測試之後，C-V曲線中的電壓與電流呈線性關係，恆電流充放電曲線則是出現了充電進去之後電卻放不掉的現象，代表電容內阻過高，從這兩點推測選用之晶片阻值過高(>4000 –cm)導致電容無法正常運作，因此本研究先將重心放在第一種製程使用單純光輔助電化學蝕刻製作矽基電極，量測後發現在混入石墨烯 5 wt%以及二氧化釕 5 wt%的固態超級電容，在0.127 A/g的電流密度下graphene/RuO2的電容性能為1.5 F/g，並且經由50次循環充放電之後，仍保有88%的電容保持率，在承受30 g的加速度之下依舊保擁有95%的電容保持率，電容需負荷超過24.5 KPa之壓應力(2×2 cm2的電容承受1 kg)後才會破損，在此狀態下電容值仍然保有原有性能之55%。

Supercapacitors have the advantages of rapid charging/discharging, high power density and long life time, applicable to the fields of mobile communications, vehicle transportation and smart grid. Most current fabrication techniques of supercapacitor utilize planar metal electrodes, appended 3D porous carbon structures such as carbon sponge, carbon aerogel or electrospun carbon fiber. By increasing the specific surface area of the carbon active materials, the power density of the supercapacitor can be improved. However, these planar metal/porous carbon structures will produce serious delamination or collapse failure under large stress, high-speed impact and vibration, making it cannot be applied to the fields which demands load-bearing and anti-shock, like defense industry, aerospace technology, and electric vehicles.
Therefore, this study will use three process to make silicon-based electrodes. The first process only uses the PAECE process, in the case of 10 wt% HF, 1 wt% surfactant alcohol, 3.5 V bias voltage, and 8 hr etching time, a random silicon hole structure with a depth of about 222 μm can be obtained; the second process is to use lithography process and RIE technology, after defining the etching window of the array pattern, it is made by PAECE technology, in the case of 2.5 wt% HF, 1 wt% surfactant DC, 3 V bias voltage, and 2 hr etching time, a silicon structure with a depth of about 162 μm can be obtained; the third process is to first use ICP-RIE technology to make a marcoporous array structure, and then use PAECE technology to roughen the inner wall of the hole structure. The parameters are 2.5 wt% HF, 5 wt% surfactant DC, 1 V bias voltage, and 2 hr etching time. After the three porous silicon structures are completed, structure surface will then be deposited a carbon film by CVD for increasing its chemical stability and conductivity. The electrolyte will be formed by using polymer materials as substrate, mixed with graphene flakes, further doped with transition metal oxide (RuO2). Coated on the structure surface, placed the specimen in a vacuum chamber, and the polymer electrolyte is infiltrated into the porous silicon structures by means of vacuum suction, and then the solid electrolyte can be formed to achieve the development of high load-bearing and anti-shock supercapacitor, and then measure C-V curve and Galvanostatic charge/discharge curve by potentiostat.
Since the silicon-based electrode using the second process encounters the problem of excessive ridgeline etching during the mass production of the structure, it is not suitable for the production of supercapacitors. The third process encounters a linear relationship between voltage and current in C-V curve after the assembly test. The GCD curve shows the phenomenon that the current cannot be discharged after charging, which means that the internal resistance of the capacitor is too high. From these two points, it is speculated that the selected chip resistance is too high and the capacitor cannot operate normally. Therefore, this research focuses on the first process using pure PAECE to make silicon-based electrodes. The capacitance of 5 wt% graphene and 5 wt% RuO2 is 1.5 F/g at 0.127 A/g. And 88% of the capacitance retention rate is still maintained at 50th cycle, and 95% of the capacitance retention rate is still maintained under the acceleration of 30 g. The capacitor load will not be damaged until it exceeds 24.5 kPa, and the capacitance value still retains 55% of the original performance.

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