隨著毫米波頻段的發展，在相位陣列(Phase Array)架構的射頻接收機中，混頻器(Mixer)和可變增益放大器(Variable Gain Amplifier)為重要的元件。由於互補式金氧半導體製程(CMOS)的進步，使得CMOS具有低功率消耗、低成本及高整合度的優勢。本論文將使用標準65-nm 1P9M互補式金屬氧化物半導體製程(Standard 65-nm 1P9M CMOS process)，實現28 GHz鏡像訊號抑制降頻器與2-6 GHz可變增益放大器，最後整合兩電路，實現寬頻鏡像訊號抑制接收機。
第一個電路為28 GHz鏡像訊號抑制混頻器，為一種降頻器。將RF訊號和LO訊號混和成IF訊號，使用的技術為I/Q訊號調變(I/Q Modulator)。RF訊號使用威爾京生功率分配器(Wilkinson Power Divider)將訊號分配到I 路徑和Q 路徑降頻器，並且藉由給予兩顆混頻器LO正交訊號和RF訊號，將兩個訊號透過馬相巴倫轉成四相位訊號合成。輸出IF端使用多相位濾波器(Poly Phase Filter)將四相位輸出訊號合成差動訊號。當電晶體閘極偏壓為0.3 V，LO驅動功率為3 dBm時，頻帶為24 ~ 27 GHz，轉換增益(Conversion Gain)範圍為-24 ± 0.3 dB，鏡像拒斥比(Image Rejection Ratio)皆小於-30 dBc。1-dB增益壓縮點之輸入功率〖IP〗_1dB約為-2 dBm。整體功率消耗約為0 mW。整體晶片佈局面積為745μm×770μm(含PAD)和620μm×660μm(不含PAD)。
第二個電路為2-6 GHz可變增益放大器，第一級為電壓緩衝放大器(Voltage Buffer)，電路核心使用Inverter Buffer，第二級使用共源級組態(Common Source Mode)。可變方式採用電流控制架構(Current Steering)，透過類比控制技術，使放大器增益可變。當供應電壓V_DD為1.2 V且V_C= 0 V時，增益約為5.29 dB ~ 20.82 dB，可變增益範圍約有15.53 dB。1-dB增益壓縮點之輸出功率〖OP〗_1dB約為3.8 dBm。整體功率消耗約為43.2 mW。整體晶片面積為665μm×770μm(含PAD)和545μm×595μm(不含PAD)。
第三個電路為毫米波寬頻鏡像訊號抑制接收機，由上述兩電路整合實現鏡像訊號抑制接收機。將混頻器混頻後的結果透過可變增益放大器放大，並透過可變技術配合系統產生不同轉換增益，讓此系統有足夠的轉換增益(Conversion Gain)。當電晶體閘極偏壓為0.3 V，LO驅動功率為3 dBm，供應電壓V_DD為1.2 V且V_C= 0 V時，頻帶為23 ~ 29 GHz，轉換增益(Conversion Gain)範圍為-0.5± 0.5 dB，鏡像拒斥比(Image Rejection Ratio)在此頻段皆小於-30 dBc。1-dB增益壓縮點之輸入功率〖IP〗_1dB約為-1 dBm。整體功率消耗約為43.2 mW。整體晶片面積為1405μm×770μm。

As the progress of the Millimeter Wave band applications, Variable Gain Amplifiers (VGA) and Mixers play important roles in the Phased-Array Radio Frequency Transceiver. Because of the breakthrough of Complementary Metal-Oxide Semiconductor (CMOS), CMOS technologies own the advantages of low power consumption, low cost and high integration. In this thesis, we implemented a 28 GHz IR Mixer and a 2-6 GHz VGA with standard 65-nm 1P9M CMOS process, and then both of the designs were a broadband image rejection receiver.
The first circuit is a 28 GHz image rejection mixer. The IF signal is mixed by RF signal and LO signal and implemented by I/Q demodulation. The RF signal will be divided into two mixers by Wilkinson Power Divider, and the LO signals in quadrature phase are injected into these mixers are converted into quadrature signal by Marchand Balun through giving two mixers LO Orthogonal signal and RF signal. The output IF port uses the Poly Phase Filter to combined quadrature signal into differential format. The demodulation was operated with gate bias of 0.3 V and LO Power of 3 dBm, and has a measured conversion gain of -24±0.5 dB from 24 GHz to 27 GHz. The input power of -1 dBm at 1-dB gain compression point (〖IP〗_1dB). The DC power consumption is 0mW. The chip size is 745μm×770μm with PAD and 620μm×660μm without PAD.
The second circuit is a 2-6 GHz VGA. The first stage is voltage buffer, and buffer core is inverter buffer. The second stage utilize Common Source topology with Current Steering techniques. The amplifier gain is controlled by analog control. When the supply voltage is 1.2 V, the amplifier has a maximum gain of 20.82 dB with a gain variation of 15.53 dB. The output power of 3.84 dBm at 1-dB gain compression point (〖OP〗_1dB). The DC power consumption is 43.2 mW. The chip size is 665μm×770μm with PAD and 545μm×595μm without PAD.
The third circuit is a mmWave Broadband Image Rejection Receiver. The two circuits mentioned above are implemented as an Image Rejection Receiver. Being beneficial from the demodulation cascaded by the proposed VGA, the receiver has a conversion gain range of 10.6 dB for actual system applications. The demodulation was operated with gate bias of 0.3 V and LO Power of 3 dBm, and has a measured conversion gain of -0.5±0.5 dB from 23 GHz to 29 GHz, and Image Rejection Ratio are less then -30 dBc from 23 GHz to 29 GHz. The input power of -1 dBm at 1-dB gain compression point (〖IP〗_1dB). The DC power consumption is 43.2 mW, and the chip size is 1405μm×770μm。

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