以熱電材料所製作之主動式致冷晶片，具有體積小、低成本、無污染、高壽命及易整合於IC元件等優點，已成為目前各式散熱研究中所重視的議題。然而，傳統的熱電散熱技術面臨了不易微小化與整合化的缺點，又面臨高密度積體電路所需之高散熱需求的挑戰，已無法負荷未來電子元件的散熱需求。因此，本研究期望以金屬輔助化學蝕刻之矽奈米線陣列做為熱電材料，配合半導體相關製程製作微型致冷晶片，以此簡易、低成本且無汙染之製程技術，實現以奈米結構來降低熱傳導率進而提升熱電優值，以改善傳統熱電材料所遇到之瓶頸，達到改善微型熱電晶片致冷效率之目標。
實驗結果顯示，以黃光微影製程與結合界面活性劑的濕式TMAH蝕刻技術，可成功於低阻值的n型(0.01-0.02 ohm-cm)與p型(0.001-0.005 ohm-cm)晶片表面，製作出凸角完整之平台微結構，此平台結構區域以金屬輔助化學蝕刻技術製作矽奈米線陣列結構，並測試出最佳的蝕刻參數。
金屬輔助化學蝕刻具有可在室溫進行製程、無須通電、大面積製造，也不需要昂貴的儀器設備，以低成本之方式即可完成矽奈米線的製作。其中，n型矽以4.6 M氫氟酸和0.02 M硝酸銀的混合溶液，在蝕刻時間為20 分鐘後，矽奈米線長度約為5-6 um，直徑約為160-200 nm，深寬比約為30-31；p型矽的部分以4.6 M氫氟酸和0.017 M硝酸銀的混合溶液，在蝕刻時間15分鐘後，奈米線長度約為4-5 um，直徑約為50-100 nm，深寬比約為50-80。
將凸塊平台結構圖案化後，為避免銀沉積太厚而覆蓋，導致氫氟酸無法順利將二氧化矽溶解，因此利用沉積銀金屬與蝕刻矽兩個階段分別進行的步驟，製作高深寬比之矽奈米線。第一階段為沉積銀金屬，皆以4.6 M氫氟酸和0.005 M硝酸銀，第二階段為蝕刻矽奈米線結構，n型矽以4.6 M氫氟酸和0.11 M雙氧水，50組p-n結構之沉積時間為1分鐘，蝕刻時間為 15 min，矽奈米線直徑約為80-150 nm，長度約為5-6 um，深寬比約為40-60；100組p-n結構之沉積時間為30秒，蝕刻時間為 15 min，矽奈米線直徑約為50-100 nm，長度約為7-8 um，深寬比約為80-140。蝕刻完後浸泡於10%的氫氟酸10-15分鐘，可去除矽奈米線外層之氧化物。完成n型與p型矽奈米線的製作後，期望日後能在SOI晶片上實現以矽奈米線作為熱電材料，製作高性能微型熱電致冷元件的目標。

Active cooling chips fabricated from thermoelectric materials have the advantages of small size, low-cost, non-polluting, high life, and easily integrated into the IC components, etc., which have been received much attention on the issues of heat dissipation research. However, the conventional thermoelectric cooling technology is facing the drawbacks of difficult miniaturization and integration. Moreover, it also must face the high cooling challenges in high density integrated circuits, that the need of high heat dissipation has been unable to be satisfied. Therefore, it is expected in this study to use metal-assisted chemical etching (MAE) for fabricating silicon nanowires (SiNWs) array served as thermoelectric materials, which will be used to fabricate the micro thermoelectric cooling chips by integrating semiconductor-related processes. This novel process has the characteristics of simple, low-cost, and no pollution, which can realize nano-structures for lowering thermal conductivity and thus enhancing the figure of merit. Such SiNWs will have an aid in improving the encountered bottlenecks of conventional thermoelectric materials, and promote the efficiency of micro thermoelectric cooling chip.
Experimental results show that the mesa arrays, with non-undercutting convex corners, have been successfully fabricated using low-resistance n-type (0.01-0.02 ohm-cm) and p-type (0.001-0.005 ohm-cm) silicon wafer by combining photolithographic process and TMAH-surfactant wet etching technique. Then the silicon nanowires were produced in the platform area of mesa by metal-assisted chemical etching (MAE) technique, and the optimal etching parameters also have been acquired. MAE has the advantages of room-temperature process, no electricity needed, large-area production, and no expensive equipment required, the silicon nanowires can be fabricated with such a low-cost process. The silicon nanowires were produced on n-type silicon with low resistance under 4.6 M HF and 0.02 M AgNO3 solution for etching 20 min, their length and diameter are about 5-6 um and 160-200 nm, respectively, the ratio of depth to width ratio is about 30-31; similarly, the silicon nanowires were produced on p-type silicon with low resistance under 4.6 M HF and 0.017 M AgNO3 solution for etching 15 min, their length and diameter are about 4-5 um and 50-100 nm, respectively, the ratio of depth to width ratio is about 50-80.
As long as the structures of salient platform have been patterned, the excessive thickness of deposited silver will cover the surface of specimen, and make silicon dioxide not be dissolved in HF solution. Therefore, a two-step process, first depositing silver metal and then etching silicon, was used to produce high-aspect-ratio SiNWs. At first period, a 4.6 M HF and 0.005 M AgNO3 mixed solution was used to deposit silver metal; at second period, a 4.6 M HF and 0.11 M H2O2 mixed solution was used to etch SiNWs. The SiNWs with a diameter of about 80-150 nm, a length of about 5-6 um, a depth to width ratio of about 40-60 have been produced under n-type silicon with low-resistance, 50 pairs of p-n thermoelectric structure, silver deposition time of 1 min, and etching time of 15 min. Similarly, the SiNWs with a diameter of about 50-100 nm, a length of about 7-8 um, a depth to width ratio of about 80-140 also have been produced under n-type silicon with low-resistance, 100 pairs of p-n thermoelectric structure, silver deposition time of 30 sec, and etching time of 15 min. SiNWs must be immersed in 10% diluted HF for 10-15 min, it is necessary to remove the silicon oxide layer formed on the periphery of SiNWs. Once completing the n-type and p-type SiNWs, it is expected that micro thermoelectric cooling (uTEC) device can be fabricated using SOI substrate in the future. The SiNWs served as thermoelectric materials will significantly promote the thermoelectric performance of uTECs, and increase their application potentials.

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