本文提出了一種使用數位增強型架構的二階ΔΣ調變器搭載多位元循序漸進式量化器。與傳統的CIFF相比，這種新架構不需要在量化器前端增加類比加法器，因此比較器前的輸入擺幅變小，降低諧波失真，同時減少加法器電路的功耗。此外，傳統的數位前饋模型會因前饋量化器而引入額外的量化雜訊，造成訊號量化雜訊比顯著降低，本研究以增加(1-z-1)/K來消除這些額外的量化雜訊，並維持數位前饋原有的優點。
為了速度與輸出擺幅的考量，第一級積分器使用摺疊疊接轉導放大器(folded-cascode OTA)，其輸入級操作在弱反轉區，如此能降低輸入參考雜訊(input-referred noise)。第二級積分器的輸出擺幅極小，放大器規格較為寬鬆，因此使用自給式偏壓轉導放大器(self-biased OTA)。該電路採用TSMC 0.18-um 1P6M CMOS製程技術。晶片核心面積為0.419mm2，在5.25 MHz取樣頻率和20 kHz頻寬下，最佳效能SNDR為83.67 dB，ENOB為13.61-bit。在使用1.4V供應電壓下功率消耗為528.9 μW，效能指標FoMSNDR達到159.4 dB。

This thesis presents a second-order ∆Σ modulator using digital-enhanced architecture and multi-bit SAR-assist quantizer. Compared to the traditional cascade integrators with distributed feedforward (CIFF) structure, this new architecture does not require an analog adder at the front end of the quantizer, which reduces the input swing before the comparator, thereby lowering harmonic distortion and reducing the power consumption of the adder circuit. Furthermore, traditional digital feedforward delta-sigma modulators suffer from additional quantization noise due to the feedforward quantizer, significantly reducing SQNR. This study compensates for the additional quantization noise by incorporating (1-z-1)/K while maintaining the original advantages of digital feedforward.
In order to consider speed and output swing, the first-stage integrator employs a folded-cascode OTA with its input stage operating in the weak inversion region, thereby reducing input-referred noise. Since the second-stage integrator has a minimal output swing, and the OTA specifications are relatively loose, so a self-biased OTA is employed. The circuit is implemented using the TSMC 0.18-μm 1P6M CMOS process. Its core area is 0.419 mm², achieving a peak SNDR of 83.67 dB and an ENOB of 13.61-bit at a 5.25 MHz sampling frequency and 20 kHz bandwidth. Under a 1.4V supply voltage, the power consumption is 528.9 μW, yielding a FoMSNDR of 159.4 dB.

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