研究生: |
張元俊 Chang, Yuan-Jyun |
---|---|
論文名稱: |
可執行快速特徵擷取之多通道低功率棘波分類電路設計 Low-Power Architecture for Multichannel Spike Sorting Circuits Based on Fast Feature Extraction |
指導教授: |
黃文吉
Hwang, Wen-Jyi |
學位類別: |
碩士 Master |
系所名稱: |
資訊工程學系 Department of Computer Science and Information Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 中文 |
論文頁數: | 64 |
中文關鍵詞: | 棘波分類 、棘波偵測 、特徵擷取 、特殊應用積體電路 |
DOI URL: | https://doi.org/10.6345/NTNU202204321 |
論文種類: | 學術論文 |
相關次數: | 點閱:72 下載:3 |
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本研究旨在於設計與合成一可植入於腦部之棘波分類晶片。根據植入於腦部的需求,晶片體積過大則會壓迫腦部,晶片功耗太高則會提高晶片溫度,如此必然會傷害到腦內細胞,因為以上兩個原因,此晶片設計將會著重於其面積以及功耗。
本研究提出以NEO運算法則為基底的棘波偵測器和以本論文提出之特徵擷取法則為基底的特徵擷取器,並藉由共享架構上的運算單元,進而設計出低功率、低面積的電路架構。本研究亦將電路實作於ASIC流程上,相較FPGA開發,ASIC在調整晶片的面積及功耗顯得更有彈性。為了降低功耗,本研究亦導入clock gating技術,進一步降低晶片的耗電量。
本論文於最後提出電路架構之分析,根據分析結果,選出數組參數進行面積及功耗分析。證明本研究設計之晶片比起其他現有的架構,有著非常突出的面積及功耗表現,並有著與現有架構差不多的分類效果。本論文也會簡單討論使用本架構之特徵擷取法與現有之PCA演算法、GHA演算法與Zero crossing演算法比較。
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