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研究生: 張元俊
Chang, Yuan-Jyun
論文名稱: 可執行快速特徵擷取之多通道低功率棘波分類電路設計
Low-Power Architecture for Multichannel Spike Sorting Circuits Based on Fast Feature Extraction
指導教授: 黃文吉
Hwang, Wen-Jyi
學位類別: 碩士
Master
系所名稱: 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 64
中文關鍵詞: 棘波分類棘波偵測特徵擷取特殊應用積體電路
DOI URL: https://doi.org/10.6345/NTNU202204321
論文種類: 學術論文
相關次數: 點閱:72下載:3
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  • 本研究旨在於設計與合成一可植入於腦部之棘波分類晶片。根據植入於腦部的需求,晶片體積過大則會壓迫腦部,晶片功耗太高則會提高晶片溫度,如此必然會傷害到腦內細胞,因為以上兩個原因,此晶片設計將會著重於其面積以及功耗。
    本研究提出以NEO運算法則為基底的棘波偵測器和以本論文提出之特徵擷取法則為基底的特徵擷取器,並藉由共享架構上的運算單元,進而設計出低功率、低面積的電路架構。本研究亦將電路實作於ASIC流程上,相較FPGA開發,ASIC在調整晶片的面積及功耗顯得更有彈性。為了降低功耗,本研究亦導入clock gating技術,進一步降低晶片的耗電量。
    本論文於最後提出電路架構之分析,根據分析結果,選出數組參數進行面積及功耗分析。證明本研究設計之晶片比起其他現有的架構,有著非常突出的面積及功耗表現,並有著與現有架構差不多的分類效果。本論文也會簡單討論使用本架構之特徵擷取法與現有之PCA演算法、GHA演算法與Zero crossing演算法比較。

    中文摘要 I 致謝 II 目錄 III 表目錄 IV 圖目錄 V 第一章 緒論 1 第一節 研究背景及動機 1 第二節 研究目的 6 第三節 論文架構 7 第二章 演算法介紹 8 第一節 棘波偵測演算法 8 第二節 快速特徵擷取演算法 10 第三章 電路系統架構 17 第一節 棘波分類系統之硬體架構 17 第二節 特徵擷取單元 19 第三節 NEO之棘波偵測單元 38 第四章 測試與數據分析 41 第一節 系統效能分析 41 第二節 開發環境 47 第三節 晶片規格分析 49 第四節 與其他現有系統比較 52 第五節 演算法效果分析 55 第五章 結論 59 參照文獻 61

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