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研究生： 李冠毅
Kuan-Yi Lee
論文名稱： 使用AB類/AB類開關運算放大器技術之0.7伏低功率低失真多位元三角積分調變器
A 0.7 V Low-Power Low-Distortion Multibit Delta-Sigma Modulator with Class-AB/Class-AB Switched-Opamp Technique
指導教授： 郭建宏
Kuo, Chien-Hung
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 中文
論文頁數： 111
中文關鍵詞： 三角積分調變器 、低失真 、低電壓 、開關運算放大器
英文關鍵詞： delta-sigma modulator, low-distortion, low-voltage, switched-OPAMP
論文種類： 學術論文
相關次數： 點閱：176  下載：20 
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    • 積體電路隨著製程技術的進步，已進入奈米的世界。然而在類比電路的設計與實現上卻沒有明顯受益，肇因於臨界電壓並未顯著減少，這對類比電路的設計是一大考驗。特別是低電壓電路要維持與一般電壓相同之效能是一項很大的挑戰。三角積分調變器對於類比電路元件的非理想特性不敏感，常運用於高解析度之電路，再結合超取樣技術、切換式運算放大器技術及雙取樣技術，可提升電路的性能。

    　　本論文提出在供應電壓為0.7V的操作下，適用於音頻範圍之三階多位元低通三角積分調變器，使用TSMC標準0.18微米製程下完成兩個電路，一為改良型三階低失真三角積分調變器，另一個為具數位加強的三階低失真三角積分調變器。操作於25 KHz的頻寬，取樣頻率為4 MHz，個別的最大SNDR各為79.94 dB和80.14 dB，功率消耗為0.8897 mW和0.566 mW。

    Though CMOS designing technology has had great improvements, analog circuit designing hasn’t gained much benefit due to the inconspicuous decrease of the threshold-voltage. This is a big problem for analog circuit designing, especially for low-voltage circuit designs, trying to maintain high performance under low voltages. Delta-Sigma Modulators have low sensitivity on non-ideal characteristics of analog circuits, so they’re usually designed for high-resolution systems. For high performance, oversampling, switched-OPAMP, and double-sampling techniques are applied.

    This thesis presents a 0.7V third-order multi-bit low-pass delta-sigma modulator. We realize two modulators by TSMC 0.18um CMOS standard process: modified and digitally enhanced third-order low-distortion delta-sigma modulator. Both operate under 25KHz bandwidth and 4MHz sampling frequency, with 79.94 dB and 80.14dB SNDR. Total power dissipation are 0.8897 mW and 0.566 mW respectively.

    中文摘要 II 英文摘要 III 誌　　謝 IV 目　　錄 V 表 目 錄 X 圖 目 錄 XI 第一章　　緒論 1 1.1　　研究動機 1 1.2　　論文組成 2 第二章　　三角積分調變器概論 3 2.1　　前言 3 2.2　　性能衡量標準 4 2.2.1　解析度 4 2.2.2　信號雜訊比 4 2.2.3　信號雜訊失真比 5 2.2.4　無雜波干擾之動態範圍 5 2.2.5　動態範圍 5 2.3　　量化器 6 2.3.1　一位元量化器 6 2.3.2　多位元量化器 7 1.Mid-rise量化器 8 2.Mid-tread量化器 8 3.非理想的多位元量化器 9 2.3.3　量化誤差 10 2.3.4　量化誤差的線性模型 11 2.4　　取樣定理 12 2.5　　超取樣技術 13 2.6　　三角積分調變器的雜訊移頻 14 2.6.1　一階雜訊移頻 15 2.6.2　二階雜訊移頻 18 1.傳統型架構 19 2.低失真架構 20 3.比較傳統型架構與低失真架構 21 2.6.3　高階雜訊移頻 22 1.單迴路架構 24 2.串疊架構 25 第三章　　低電壓下三角積分調變器的電路元件設計 27 3.1　　前言 27 3.2　　低電壓設計 27 3.2.1　低臨界電壓製程 28 3.2.2　電壓增強技術 28 3.2.3　靴帶式開關電路 29 3.2.4　使用靴帶式開關為取樣開關電路 30 3.3　　交換電容式電路 32 3.3.1　反相積分器 32 3.3.2　非反相積分器 33 3.4　　開關運算放大器的初始原理 34 3.5　　使用雙取樣技術之開關運算放大器積分器電路 36 3.6　　AB類/AB類開關運算放大器 38 3.6.1　AB類輸入對的工作原理 40 3.6.2　共模回授電路 42 3.6.3　偏壓電路 43 3.6.4　AB類/AB類運算放大器電路的模擬結果 44 3.7　　多位元量化器 45 3.7.1　適用於低電壓的多位元量化器 45 3.7.2　適用於低電壓的比較器 46 3.7.3　多位元量化器電路的模擬結果 47 3.8　　動態元件不匹配 48 3.8.1　資料權重平均法 49 3.8.2　時脈平均演算法 50 3.9　　非重疊時脈產生器 51 第四章　　低電壓下改良式三階低失真三角積分調變器 52 4.1　　改良式三階低失真三角積分調變器之系統架構 52 4.1.1　三角積分調變器之輸入前饋路徑架構 52 4.1.2　傳統三階低失真三角積分調變器 53 4.1.3　改良式三階低失真三角積分調變器 53 4.1.4　改良式三階低失真三角積分調變器之係數決定 54 4.2　　系統架構的MATLAB模擬 56 4.2.1　系統架構的模擬與分析 57 4.2.2　取樣電容之決定 58 4.2.3　運算放大器之有限增益 60 4.2.4　時脈抖動需求 60 4.2.5　系統架構的非理想模擬 61 4.3　　系統架構的HSPICE模擬 62 4.3.1　系統中AB類/AB類運算放大器電路的模擬結果 64 4.3.2　系統中積分器電路的模擬結果 65 4.3.3　系統架構的模擬結果 65 4.3.4　佈局與晶片腳位配置 65 4.4　　實驗結果 68 4.4.1　輸入訊號源與輸入終電路 68 4.4.2　供應電壓的產生 69 4.4.3　參考電壓的產生 70 4.4.4　濾波器槽 70 4.4.5　量測結果 70 4.5　　結論 74 第五章　　具數位加強之低電壓低失真三角積分調變器 75 5.1　　具數位加強之低失真三角積分調變器之系統架構 75 5.1.1　具數位加強之三角積分調變器架構 75 5.1.2　具數位加強之三階低失真三角積分調變器 76 5.2　　系統架構的MATLAB模擬 77 5.2.1　系統架構的模擬與分析 78 5.2.2　與AFF架構的比較 79 5.2.3　系統架構的非理想模擬 80 5.3　　系統架構的HSPICE模擬 81 5.3.1　系統中AB類/AB類運算放大器電路的模擬結果 83 5.3.2　系統中積分器電路的模擬結果 84 5.3.3　系統架構的模擬結果 84 5.3.4　佈局與晶片腳位配置 84 5.4　　實驗結果 87 5.5　　結論 89 第六章　　總結與未來展望 90 6.1　　總結 90 6.2　　未來展望 91 參考文獻 92

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