隨著半導體製程技術的進步，積體電路的元件尺寸能夠設計得越來越小，從而大幅度縮減晶片的面積，相對地供應電壓也能下降，以降低晶片的功率消耗。在當今技術的進步下，低功耗、高效能晶片不斷地推出，市場對此的需求也越來越高。類比數位轉換器有多種實現方式，其中三角積分調變器相較於其他類比數位轉換器，具有獨特的超取樣技術和雜訊移頻特性，不僅能降低非禮想效應對電路的影響，還能滿足市場對高效能、高解析度、低功耗的電路的需求。因此，該架構在在音頻及通訊領域得到廣泛應用。
本文提出了一個1.4V的二階反向器基底的三角積分調變器，採用雜訊移頻逐次逼近式的方式實現類比數位轉換器，並採用了二階CIFF低失真架構。使用了自己式偏壓反向器基底積分器，不需要額外的共模回授和偏壓電路，從而改善了傳統運算放大器高功耗和佔用面積的缺點。此外，為了降低開關時脈饋入對電路影響，提出了分裂電容的方法，以提高運算放大器輸入電壓的穩定性和並減少開關寄生電容對效能的影響。提出的架構使用T18 0.18um 1P6M CMOS 製程技術。晶片核心面積為0.098mm2，此電路在取樣頻率4.5MHz，頻寬為20kHz，最佳效能為SNDR 88.29dB，SNR為88.63dB，ENOB為14.37 Bit。在1.4V供應電壓下功率消耗為113.1uW。

With the advancement of semiconductor fabrication technology, integrated circuit components can be designed to be smaller and significantly reduce chip area. Consequently, the supply voltage can also be lowered to reduce power consumption. With the progress in technology, there is a growing demand in the market for low-power, high-performance chips. Analog-to-digital converters (ADCs) can be implemented in various ways, and among them, the delta-sigma modulator (DSM) stands out due to its unique oversampling technique and noise-shaping characteristics. It not only reduces the impact of quantization noise on the circuit but also meets the market demand for high-performance, high-resolution, and low-power circuits. Therefore, this architecture finds extensive applications in the fields of audio and communication.
This paper proposes a second-order delta-sigma modulator based on a 1.4V inverted-amp-based integrator, implementing an analog-to-digital converter (ADC) using a noise-shaping successive approximation approach. The architecture employs a second-order CIFF structure. It utilizes self-biased inverted-amp-based integrators, eliminating the need for additional common-mode feedback and biasing circuits, thereby addressing the drawbacks of high power consumption and large footprint associated with conventional operational amplifiers. Additionally, to mitigate the impact of clock feedthrough on the circuit, a split-capacitor technique is introduced to enhance the stability of the operational amplifier input voltage and minimize the effects of switch parasitic capacitance on performance. The proposed architecture is implemented using T18 0.18um 1P6M CMOS process technology. The core area of the chip is 0.098mm2. Under the sampling frequency of 4.5MHz and a bandwidth of 20kHz, the optimal performance achieved is SNDR of 88.29dB, SNR of 88.63dB, and ENOB of 14.37 bits. The power consumption is 113.1uW under a 1.4V supply voltage.

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