研究生: |
謝立文 Raymond Shieh |
---|---|
論文名稱: |
急動度限制下之定位伺服及其干擾補償方法 A Jerk-Constrained Time-Optimal Servo with Disturbance Compensation |
指導教授: |
呂有勝
Lu, Yu-Sheng |
學位類別: |
碩士 Master |
系所名稱: |
機電工程學系 Department of Mechatronic Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 英文 |
論文頁數: | 67 |
中文關鍵詞: | 急動度 、最佳時控制 、干擾估測器 |
英文關鍵詞: | jerk-constraint, time-optimal control, disturbance observer |
論文種類: | 學術論文 |
相關次數: | 點閱:127 下載:10 |
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本論文提出一種急動度限制下之定位控制及其干擾補償法,以改善系統輸出響應。在機械系統裡,急動度(加速度對時間的微分)若是太大可能會對系統造成不良的影響。故提出一急動度限制下之最佳時間定位控制法(Jerk-constrained time-optimal control, JCTOC),此控制法不僅可限制最大急動度,又可達到最佳時間控制的效果。JCTOC是利用最佳時間控制器結合一積分器與受控體,直接控制系統的急動度來做其限制。
但由於提出的JCTOC是一種高度依賴受控體模型又俱備控制法則切換的控制法,故很容易受到系統不確定性以及系統干擾的影響。故在此加入一干擾補償器(Disturbance observer, DOB)以補償干擾並降低對系統的影響。本論文主要探討的干擾估測器以積分器的方式呈現,故在此稱為積分型干擾估測器(integral disturbance observer, IDOB)。在此IDOB加入一動態補償器或內部模型原理(Internal model principle, IMP)補償器,可讓干擾估測對於不同階數的干擾有更優越的抑制效果。
本文實驗平台以一裝對稱性負載之無刷伺服馬達為受控體,並以一DSP/FPGA結合之單元為控制器,分別以C語言及VHDL撰寫。以此機台為實驗系統並實現本文提出之干擾補償及急動度限制下之最佳時間控制法,並由實驗結果證實其控制法的可行及實用性。
This paper presents an improved disturbance rejection method added to a model based time-optimal control method, in order to assure the correct system output response. In mechanical systems, the jerk (the time derivative of acceleration) may cause many unwanted results when too high. Thus, a jerk-constrained time-optimal control (JCTOC) method is proposed to not only constrain the jerk of the system, but also have a time-optimal characteristic. The JCTOC uses a time-optimal controller paired with an integrator and the system to directly constrain the jerk of the system.
But, due to the JCTOC being a highly model based control method with switching characteristics, the system uncertainties and disturbance can have an adverse effect on the output response. Thus, a disturbance observer (DOB) is added for the compensation of the disturbance. The DOB used in this paper is in an integral form, thus called an integral disturbance observer (IDOB). The IDOB is further enhanced with a dynamic compensator to provide better noise immunity and asymptotic compensation for disturbances of various orders.
This paper uses a symmetrically loaded servo motor as an experimental setup for the proposed control methods. The control kernel is a DSP/FPGA system separately programmed with C language and VHDL. Experiments of the disturbance rejection method have been conducted and proven to have better transient and steady-state responses than past approaches while fulfilling the time-optimal characteristic of the JCTOC.
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