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研究生: 華春和
論文名稱: 影像邊緣偵測之參數化FPGA架構設計
A Parameterized FPGA Architecture for Image Edge Detection Algorithms
指導教授: 張吉正
Chang, Chi-Jeng
蕭培墉
Hsiao, Pei-Yung
學位類別: 碩士
Master
系所名稱: 工業教育學系
Department of Industrial Education
論文出版年: 2003
畢業學年度: 91
語文別: 中文
中文關鍵詞: 數位影像處理邊緣偵測參數化FPGA架構設計
論文種類: 學術論文
相關次數: 點閱:253下載:24
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  • 邊緣乃是具有相當差異之局部特性所構成的邊界,此局部特性包含灰階值、顏色、紋理結構…等。所以在許多的應用場合中,皆以影像邊緣偵測作為影像前處理的過程中一個最重要的步驟。在許多情形下,影像中的物件可以單獨由外型辨識出來,假如一張影像只留下邊緣部分的資訊,這樣一來不但提供了一個做影像分割的方法,也可以大量的減少影像處理及儲存的資料量。
    在本研究中對於目前最適合硬體化的邊緣偵測方法,進行演算法的整理與分析,並利用FPGA來實現影像邊緣偵測演算法的硬體架構。所提出影像邊緣偵測參數化架構,其採取的參數化的設計原則包含可以調整影像尺寸(Image Dimension),可選擇不同的邊緣運算子(Edge Operator)、梯度值運算方法(Gradient Magnitude)以及可調整邊緣影像輸出時的像素置換模式(Pixel Replace)。此硬體架構對一幅256x256 Pixels的八位元灰階影像進行邊緣偵測,只需大約1.4ms的運算時間,以相同的原始影像及參數設定,個人電腦(PC)則需要24ms才能完成全部的運算,因此本論文所提之架構的運算速度比個人電腦快了十七倍。此架構所花費的硬體資源不高,且運算速度完全符合即時影像處理的需求,將提供使用者更高之使用彈性及方便性。

    中文摘要 2 總目錄 3 圖目錄 4 第一章 緒論 6 第一章 緒論 6 第一節 前言 6 第二節 研究動機 9 第三節 研究目的 13 第四節 研究限制與範圍 13 第二章 影像邊緣偵測演算法 14 第一節 邊緣特徵 14 第二節 基本定義 15 第二節 數位影像之梯度運算 18 第三節 一階導數邊緣運算子 21 第三章 參數化設計原則 27 第一節 影像尺寸 29 第二節 邊緣運算子 29 第三節 梯度值運算方法 29 第四節 像素置換模式 30 第四章 系統架構與模組單元設計 32 第一節 系統架構 32 第二節 Pipelined FIFO 34 第三節 Delay Unit 35 第四節 Processor Network 35 第五節 Absolute Value Generator 37 第六節 Gradient Magnitude Unit 38 第七節 Thresholding Unit 39 第五章 驗測平台與實驗結果 40 第一節 驗測平台電路設計 40 第二節 實驗結果分析 41 第六章 結論 51 參考文獻 52

    [1]Danny Crookes, “Architectures for high performance image processing:The future,” Elsevier Science, Journal of systems architecture. pp 739-748, 1999.
    [2]Rafael C. Gonzalez, Richard E. Woods, Digital Image Processing, 2nd ed:Prentice Hill, 2002.
    [3]C. Torres-Huitzil, M. Arias-Estrada, “ An FPGA Architecture for High Speed Edge and Corner Detection,” Fifth IEEE International Workshop on Computer Architecture for Machine Perception, pp. 112-116, 2000.
    [4]Q. Gongyuan, S. Wood, “Edge detection using improved morphological gradient,” IEEE Signals, The Thirty-Second Asilomar Conference on Systems & Computers, vol. 2, pp.954-958, 1-4 Nov 1998.
    [5]M.B. Ahmad, Tae-Sun Choi, “Local Threshold and Boolean Function Based Edge Detection,” IEEE Transactions on Consumer Electronics, vol. 45 no. 3, pp.674-679, Aug 1999.
    [6]F. Faghih, M. Smith, “Combining Spatial and Scale-Space Techniques for Edge Detection to Provide a Spatially Adaptive Wavelet-Based Noise Filtering Algorithm,” IEEE Transactions on image processing, vol. 11, no. 9, 2002.
    [7] R.C.D.M. Tavares, C.J.N. Jr. Coelho, A.D.A. Araujo, A.O. Fernandez, “Implementation of an Edge Detection Algorithm in a Reconfigurable Computing System,” XI Brazilian Symposium on Integrated Circuit Design, 1998.
    [8]Zhigang Jin, N.L. Passos, “Predicting conditional branch outcomes on a sobel edge detecting filter,” IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 3, pp. 3192-3195, 2002.
    [9]S. Dawood, S.J. Visser, J.A. Williams, “ Reconfigurable FPGAs for real time image processing in space,” The 14th International Conference on Digital Signal Processing, vol. 2 , 2002.
    [10]A. Benedetti, A. Prati, N. Scarabottolo, “ Image convolution on FPGAs: the implementation of a multi-FPGA FIFO structure,” The 24th IEEE Euromicro Conference, vol. 1, pp. 123-130, 25-27 Aug 1998.
    [11]K. Stuart, L. SukHwan, L. Xinqiao, E.G. Abbas , “ A 10000 Frames/s CMOS Digital Pixel Sensor,” IEEE Journal of Solid-State Circuits, vol.36, no.12, 2001.
    [12]N. Kanopoulos, N. Vasanthavada,R.L. Baker,” Design of an image edge detection filter using the Sobel operator,” IEEE Journal of Solid-State Circuits, vol. 23, no. 2, pp. 358-367, Apr 1988.
    [13]M. Boo; E. Antelo, J.D. Bruguera, “ VLSI implementation of an edge detector based on Sobel operator,” The 20th EUROMICRO Conference on System Architecture and Integration, pp.506-512, 5-8 Sep 1994.
    [14]T. Aboulnasr, W. Steenaart, “ Real-time systolic array processor for 2-D spatial filtering,” IEEE Transactions on Circuits and Systems, vol. 35, no. 4, pp. 451 -455, Apr 1988.
    [15]C. Torres-Huitzil, M. Arias-Estrada, “ An FPGA Architecture for High Speed Edge and Corner Detection,”, Fifth IEEE International Workshop on Computer Architecture for Machine Perception, pp. 112-116, 2000.
    [16]Fahad M. Alzahrani, Tom Chen, “A Real-Time Edge Detector: Algorithm and VLSI Architecture,” Real-Time Imaging, vol. 3, no. 5, pp. 363-378, October, 1997,
    [17] D. Demigny, “ On optimal linear filtering for edge detection,” IEEE Transactions on Image Processing, vol. 11, no. 7, pp. 728-737, July 2002.
    [18]J. Bevington, R. Mersereau, “Differential operator based edge and line detection,” IEEE International Conference on ICASSP Acoustics, Speech, and Signal Processing , vol. 12, pp. 249 -252, Apr 1987.
    [19]E.R. Davies, “ Optimising computation of hexagonal differential gradient edge detector,” Electronics Letters , vol. 27, no. 17, pp. 1526-1527, 15 Aug 1991.

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