研究生: |
華春和 |
---|---|
論文名稱: |
影像邊緣偵測之參數化FPGA架構設計 A Parameterized FPGA Architecture for Image Edge Detection Algorithms |
指導教授: |
張吉正
Chang, Chi-Jeng 蕭培墉 Hsiao, Pei-Yung |
學位類別: |
碩士 Master |
系所名稱: |
工業教育學系 Department of Industrial Education |
論文出版年: | 2003 |
畢業學年度: | 91 |
語文別: | 中文 |
中文關鍵詞: | 數位影像處理 、邊緣偵測 、參數化 、FPGA架構設計 |
論文種類: | 學術論文 |
相關次數: | 點閱:267 下載:24 |
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邊緣乃是具有相當差異之局部特性所構成的邊界,此局部特性包含灰階值、顏色、紋理結構…等。所以在許多的應用場合中,皆以影像邊緣偵測作為影像前處理的過程中一個最重要的步驟。在許多情形下,影像中的物件可以單獨由外型辨識出來,假如一張影像只留下邊緣部分的資訊,這樣一來不但提供了一個做影像分割的方法,也可以大量的減少影像處理及儲存的資料量。
在本研究中對於目前最適合硬體化的邊緣偵測方法,進行演算法的整理與分析,並利用FPGA來實現影像邊緣偵測演算法的硬體架構。所提出影像邊緣偵測參數化架構,其採取的參數化的設計原則包含可以調整影像尺寸(Image Dimension),可選擇不同的邊緣運算子(Edge Operator)、梯度值運算方法(Gradient Magnitude)以及可調整邊緣影像輸出時的像素置換模式(Pixel Replace)。此硬體架構對一幅256x256 Pixels的八位元灰階影像進行邊緣偵測,只需大約1.4ms的運算時間,以相同的原始影像及參數設定,個人電腦(PC)則需要24ms才能完成全部的運算,因此本論文所提之架構的運算速度比個人電腦快了十七倍。此架構所花費的硬體資源不高,且運算速度完全符合即時影像處理的需求,將提供使用者更高之使用彈性及方便性。
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