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研究生: 傅義全
Fu, Yi-Quan
論文名稱: 應用於高頻輸入/出端與電源端之靜電放電防護設計
ESD Protection Design for High-Frequency Input/Output Terminal and Power Terminal Application
指導教授: 林群祐
Lin, Chun-Yu
口試委員: 柯明道
Ker, Ming-Dou
張勝良
Jang, Sheng-Lyang
林群祐
Lin, Chun-Yu
口試日期: 2021/10/08
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 英文
論文頁數: 99
中文關鍵詞: 靜電放電高頻寄生電容靜電放電箝位電路正常上電源快速上電源
英文關鍵詞: electrostatic discharge (ESD), high-frequency, parasitic capacitance, power-rail ESD clamp circuit, normal power-on, fast power-on
研究方法: 實驗設計法主題分析比較研究
DOI URL: http://doi.org/10.6345/NTNU202101808
論文種類: 學術論文
相關次數: 點閱:161下載:0
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  • 隨著 CMOS 製程越來越先進,電晶體尺寸微縮,使可操作於更高的工作頻率,但會使電晶體對於靜電越來越敏感,靜電放電是影響積體電路可靠度的主要因素,須設計出高耐受度的靜電放電防護電路,避免積體電路遭受靜電轟擊而損壞。
    靜電放電防護通常設計於輸入/出端,當應用於高頻積體電路中,須具備較低的寄生電容,否則會影響高頻電路的特性,而傳統防護元件選擇簡單的二極體,但操作頻率越來越高時,造成高頻電路特性大幅衰減,因此本論文提出藉由電阻串並聯方式使二極體產生的負載減少,並採用 CMOS 製程實踐,透過各項量測證實在單位面積下有低的高頻訊號流失和擁有足夠高的靜電放電防護能力。
    因靜電也會由電源端進內部電路,所以必須有電源箝制防護電路,而電源箝制防護電路中的觸發機制被用來判斷靜電是否發生,但當內部電路上電的時間常數與靜電相近時,電阻-電容充放電機制會使排放靜電的元件意外導通,造成電源端的訊號極大流失。因此,本論文使用 CMOS 製程實踐現有電源箝制電路,分析不同的靜電放電耐受度測試、正常上電與快速上電時的可行性。

    The manufacturing process becomes more advanced for high-frequency applications than before. However, the transistor is sensitive to static electricity. Therefore, it is necessary to design an electrostatic discharge (ESD) protection circuit with high ESD robustness to prevent the integrated circuit from being damaged by ESD current bombardment.
    The ESD protection device is usually designed at the input/output pad. When the internal circuits are operated at high frequency, the ESD protection device should have low parasitic capacitance. Otherwise, the ESD protection device will affect the character of the high-frequency circuit. Though the simple diodes are chosen as traditional protection component, they will cause severe signal loss at higher frequency. Therefore, the thesis proposed the RC-diode ESD protection device that is adopted CMOS process to reduce signal loss through the resistor series and parallel method. As a result, the RC-diode protection device has outstanding ESD robustness and low signal loss per unit area by various testing.
    Because the static electricity will also enter the internal circuit from the power supply terminal, the power-rail ESD clamp circuit is essential. The trigger mechanism in power-rail ESD clamp circuit is used to determine whether the static electricity occurs. However, the time constant of the internal circuit power-on and static electricity is close, the resistor-capacitor inverter mechanism will accidentally trigger the components of discharge current to cause significant power loss at the power supply terminal. Therefore, this thesis has adopted the CMOS process to fabricate present power-rail ESD clamp circuits for internal circuit. These power-rail ESD clamp circuits are analyzed under different testing methods of ESD robustness and discussed for internal circuit of normal and fast power-on feasibility.

    Acknowledgment i Abstract (Chinese) ii Abstract (English) iii Contents v List of Tables viii List of Figures x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Background of ESD 2 1.3 Component-Level Test Standards of ESD 2 1.3.1 Human-Body Model (HBM) 3 1.3.2 Charged-Device Model (CDM) 4 1.4 Consideration of Designing Whole-Chip ESD Protection Circuits 5 1.4.1 ESD Protection Design Window 6 1.5 ESD Protection Components for High-Frequency Application 7 1.5.1 Dual Diodes [16] 8 1.5.2 Dual Stacked Diodes [17] 9 1.5.3 LC Tanks [18] 10 1.6 Power-Rail ESD Clamp Circuits 11 1.6.1 Power-Rail ESD Circuit with Resistor-Capacitor Inverter Mechanism [19] 13 1.6.2 Power-Rail ESD Circuit with Diode-Trigger Mechanism [20] 14 1.6.3 Power-Rail ESD Circuit with Positive-Feedback Mechanism [21] 15 1.6.4 Power-Rail ESD Circuit with Double-Detector Mechanism [22] 16 1.7 Organization of This Dissertation 17 Chapter 2 Resistance-Capacitance Diode for High-Frequency Application 18 2.1 Traditional Dual-Diode Design 18 2.2 Traditional LC-Tank Design 22 2.3 Proposed RC-Diode Design 27 2.4 Measurement Results 35 2.4.1 High-Frequency Performance 36 2.4.2 Transmission-line pulsing (TLP) Measurement 41 2.4.3 HBM Robustness 48 2.4.4 Very-Fast Transmission-line pulsing (VF-TLP) Measurement 50 2.5 Comparison and Discussion of This Test Chip 52 2.6 Comparison of Proposed RC Diode and Literature 58 2.7 Summary 59 Chapter 3 ESD Clamp Circuits for Power Terminal Application 60 3.1 Power-Rail ESD Clamp Circuits 60 3.1.1 Resistor-Capacitor Inverter Mechanism [19] 61 3.1.2 Diode-Trigger Mechanism [20] 63 3.1.3 Positive-Feedback Mechanism [21] 65 3.1.4 Double-Detector Mechanism [22] 68 3.2 Simulation Results 70 3.2.1 ESD-like waveform condition 70 3.2.2 Normal Power-on Condition 75 3.2.3 Fast Power-on Condition 77 3.3 Measurement Methods and Results 79 3.3.1 Transmission-line pulsing (TLP) Measurement 80 3.3.2 Very-Fast Transmission-line pulsing (VF-TLP) Measurement 81 3.3.3 ESD Robustness 82 3.3.4 Power Loss under Fast Power-on Event 84 3.4 Comparison of This Test Chip 85 3.5 Discussion of This Test Chip 87 3.6 Summary 90 Chapter 4 Conclusion and Future Work 91 4.1 Conclusion 91 4.2 Future Work 93 Reference 96

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