隨著網路傳輸速度及無線通訊的需求增加，具寬頻、高速傳輸優點之毫米波波段的重要性日趨重視。在此考量到CMOS製程之低成本，高整合性可達到系統單晶片之優勢，本論文所設計之兩顆電路皆採用個別採用標準90-nm、65-nm 金氧半製程進行設計製造。
第一顆電路為應用於衛星通訊頻段17-21GHz之低雜訊放大器，採用TSMC 標準 90-nm CMOS製程所製造設計。此低雜訊放大器第一級放大器使用共源極放大器(Common Source)串接具有中和電容之CS 差動對，此電路使用固定功率之雜訊與阻抗共匹配(PCSNIM)-低雜訊條件下實現低功率損耗、電流再利用技術-兩級放大器共享來自供應電源的直流電流可顯著降低功耗，級間與輸出匹配則採用於矽基製程上設計之中心抽頭變壓器實現以降低電感匹配所浪費的面積。量測結果顯示出，在供應電壓VDD=1.5V下，僅有3mW的功率消耗-2mA的靜態電流，在20.4GHz下具15.57dB的小訊號功率增益，1-dB頻寬為17.5~21.7GHz。線性度量測部分，在19GHz之OP1dB=-9.4dBm。雜訊指數量測部分，在操作1dB頻寬內雜訊指數小於2.4dB，在18GHz可達到最低2dB的雜訊指數，包括DC pad與RF pad之整體晶片面積為665μm×687μm。與已發表之國際期刊相比，此雜訊指數僅2dB、15.57小訊號增益、功耗3mW之90nm CMOS LNA，於17-21GHz操作頻段附近之全積體化互補式金氧半製程中，是世界上第一個達到最低雜訊指數之LNA，且依據FOM性能指標，此低雜訊放大器高達20.1。
第二個電路為操作於基頻頻段3-4GHz之低雜訊可變增益放大器VGLNA，採雙端輸入輸出架構，共串接兩級放大器以提高功率增益，第一、二級放大器分別採取電壓緩衝器(Voltage Buffer)與共源極(Common Source)放大器。使用Current Steering-數位控制搭配基極偏壓(Body Bias)之架構調變主放大器增益。採用標準65-nm 1P9M CMOS製程設計，總晶片面積包括DC Pad與RF Pad為695μm×740μm，在供應電壓VDD=1V，VGS=0.65V，基極偏壓VB=1V下，量測小訊號功率增益部分在主頻段3.5GHz時=23.24dB，可變增益範圍GCR=32.77dB。在頻率3.5GHz，1 dB增益壓縮點的輸出功率OP1dB=3.45dBm。雜訊量測部分，在3GHz之NF=1.9dB。

As the demand of high-speed transmission and wireless communication increases, the importance of the millimeter-wave band that has advantages of broadband and high-speed transmission is being increasingly valued. Considering the advantages of low cost and high integration capabilities of CMOS technology that can achieve system-on-chip(SOC), two circuits in this paper are using standard 90-nm and 65-nm CMOS processes to design and manufacture.
The first circuit is Low noise amplifier applied to 17-21GHz satellite communication and fabricated on TSMC's 90nm CMOS process. The first stage of this LNA utilizes common-source (CS) and series the second stage using neutralized differential common-source stage (CS). This circuit uses Power-Constrained Simultaneous noise and input matching (PCSNIM)-low power consumption realized at low noise figure, current-reuse technology-two stage amplifiers share the DC current from power supply to significantly decrease power consumption, inter-stage and output matching use center-tapped transformers based on silicon-based process to reduce area wasting of inductor matching. Measurement results show that the power consumption is only 3mW-2mA quiescent current, the small signal power gain is 15.57 at 20.4GHz, and the 1-dB bandwidth is 17.5~21.7GHz. The linear measurement, OP1dB is -9.4dBm at 19GHz. Noise Figure measurement, the NF is less thwn 2.4dB within 1-dB bandwidth, and the lowest NF is 2dB at 18GHz. The overall chip area including the DC Pad and RF Pad is 665μm×687μm. Compared with published international journals, this 90nm CMOS LNA with only 2dB NF, small-signal gain 15.57dB, and only 3mW power consumption is the best in a fully integrated CMOS process near the operating frequency band of 17-21GHz. This LNA first achieves the lowest NF in the world (near 19 GHz), and according to the FOM performance index, this LNA is as high as 20.1.
The second circuit is low noise variable gain amplifier (VGLNA) operating in base frequency band 3-4GHz. It adopts a double-ended input and output structure, and series two-stage amplifier to increase the power gain. The first and second amplifiers adopt voltage buffer and CS amplifier respectively. Use Current Steering-digital control and body bias to modify the gain of the main amplifier. The standard 65-nm 1P9M CMOS process design is adopted. The total chip area including DC Pad and RF Pad is 695μm×740μm. Under VDD=1V, VGS=0.65V, and body bias VB=1V of the supply Voltage, the small signal power gain is 23.24dB at the main frequency 3.5GHz, and the GCR is 32.77dB. At 3.5GHz, the output power at the 1-dB gain compression point, OP1dB is 3.45dBm. Noise figure is 1.9dB at 3GHz.

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