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研究生: 黃正誼
論文名稱: 內嵌CMOS 影像感測擷取模組及影像濾波器之FPGA 平台設計
指導教授: 張吉正
Chang, Chi-Jeng
黃奇武
Huang, Chi-Wu
學位類別: 碩士
Master
系所名稱: 工業教育學系
Department of Industrial Education
論文出版年: 2004
畢業學年度: 92
語文別: 中文
論文頁數: 80
中文關鍵詞: CMOS 影像感測器迴旋運算器空間濾波器心臟壓縮式陣列硬體排序器現場式可程式閘陣列
論文種類: 學術論文
相關次數: 點閱:366下載:5
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  • 隨著影像感應晶片的製成技術進步,未來電子、資訊產品也將漸漸把
    影像服務視為基本配備,例如:數位相機、視訊會議、玩具…等等。目前
    影像感應晶片的製程方式分為CCD 與CMOS 兩類,由於CMOS 影像感
    測晶片限於材料特性限制,影像品質一直略遜於CCD 影像感測晶片,若
    使用軟體改善CMOS 影像感測晶片的影像品質,將造成系統速度變慢,
    若採用額外的處理器,使得成本提升皆不划算。因此提出整合CMOS 影
    像感測晶片之”擷取影像”與”影像濾波” FPGA 發展平台。藉由FPGA 硬體
    的速度,可同時擷取影像並選擇進行線性(高通、低通與高斯平滑濾波)或
    非線性(最大值、中值與最小值濾波),將雜訊予以濾除。
    在線性濾波器方面,改善了Crookes 影像濾波器的設計,使其能以較
    少的硬體資源達成濾波效果,及充分配合FPGA 內建的Block RAM 做成
    動態大小的佇列,使得濾波器能即時地適應不同尺寸的影像大小。非線性
    的排序濾波器,則採Maheshwari 演算法為基礎,並提出與線性濾波器共
    用部分資源的方式,以減輕資體資源的花費。

    CMOS image sensors become more and more widely used today in toys,
    mobile-phones, and digital cameras. As far as speed and image qualities are
    concerned CCD image sensors are still superior to CMOS image sensors and
    are more expensive. This paper presents a FPGA version to improve CMOS
    image sensor performance.
    The ever increasing gate-count in a FPGA Chip has made it possible to
    integrate the image capturing and filtering processes into a hardware circuitry,
    providing a faster image capturing as well as noise filtering. Therefore, this
    project proposed a CMOS image sensor application of FPGA platform design
    that integrated the image capturing and many noise filtering circuits, such as
    low pass, High pass, mean, maximum, minimum, ect., which were selectable
    through different parameter setting. This FPGA chip can communicate with a
    pipelined RAM structure to process the capturing images and to enhance their
    qualities.
    Actual hardware design in this paper has made FPGA consumption very
    effective by carefully rearranged the buffers and processor elements(PEs) in
    Crooks’ linear filter, two third of the original registers can be saved. Also by
    modified Maheshwari’s nonlinear filter with sharing buffers, the buffer area is
    again reduced the half of the original size.
    According to the preliminary test, the hardware image capturing circuit in
    the FPGA might have several ten times faster than usually done by
    microprocessors (pic, 89c51 series) or by DSP chips that could demonstrate
    more favorable real time performance.

    第一章緒論......................................................................................................1 第一節研究背景......................................................................................1 第二節研究動機......................................................................................6 第三節研究目的......................................................................................7 第四節研究步驟......................................................................................8 第二章空間域影像濾波原理..........................................................................9 第一節影像平面定義............................................................................10 第二節二維影像迴旋運算....................................................................13 第三節二維影像排序濾波....................................................................17 第三章快速取像與濾波器之硬體架構與單元規劃....................................20 第一節訂定硬體功能單元....................................................................20 第二節各硬體單元組織關係................................................................22 第四章影像感應晶片相關硬體單元設計....................................................24 第一節初始化影像感應晶片單元........................................................24 第二節影像擷取單元............................................................................33 第五章影像處理相關硬體單元設計............................................................39 第一節傳統之二維影像空間濾波器硬體架構...................................39 第二節改良之二維影像空間濾波器硬體架構...................................42 第三節二維影像排序濾波器硬體架構...............................................49 第四節IPU 硬體架構設計....................................................................53 第六章參數硬體單元與傳送硬體單元........................................................56 第一節影像傳送單元硬體設計............................................................56 第二節記憶體與參數管理單元硬體設計...........................................59 第七章驗證平台與實驗結果........................................................................65 第一節驗證平台規劃............................................................................65 第二節實驗成果分析............................................................................68 第八章結論與未來展望................................................................................71 參考文獻..........................................................................................................73 附錄一測試樣本濾波成果............................................................................77

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