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研究生: 黃紹嘉
HUANG, Shao-Jia
論文名稱: 摻雜之二硫化硒層狀材料在作為場效應電晶體通道對降低源/汲極接觸電阻之研究
Study of Doping Layered-WSe2 Material as Field Effect Transistor Channel for Source/Drain Contact Resistance Reduction
指導教授: 李敏鴻
Lee, Min-Hung
鍾朝安
Jong, Chao-An
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 103
中文關鍵詞: 二硫化硒二硒化鎢二硫化鉬接觸電阻硒化
英文關鍵詞: MoS2, WS2, WSe2, Contact Resistance, Selenization
DOI URL: https://doi.org/10.6345/NTNU202204028
論文種類: 學術論文
相關次數: 點閱:119下載:0
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  • 近幾年,過渡金屬硫屬化合物因為具有能隙關係,比同樣具有二維結構的石墨烯更適合用在電晶體元件製作,因此吸引很研究學者的興趣。其中WSe2是屬於P型的半導體更特別引人關注,然而一直缺乏一個穩定可控制的摻雜技術,難度頗高。本篇將開發一個穩定可行的摻雜製程,利用共濺鍍製程技術加上後硒化處理。希望用這個方法能夠讓電晶體的載子濃度及載子遷移率提升,讓通道電阻及接觸電阻有效的降低。

    Recently, two dimensional transition metal dichalcogenides (TMDs) compounds have drawn much interest due to their potential in TFT channel application than Graphene which without bandgap. Among these 2D materials, p-type WSe2 is particularly attractive. However, precise doping of WSe2 is difficult due to the absence of a controllable doping technique. In this paper, a controllable WSe2 doping method by co-sputtering process followed by post selenization treatment is demonstrated. Using this technique, high acceptor doping concentration and good hole mobility were obtained. Low sheet resistance and contact resistance were obtained.

    中文摘要 I Abstract II 致謝 III 目錄 V 圖目錄 IX 表目錄 II 第一章 緒論 1 1-1-1 魚鰭式場效應電晶體(Fin Field Effect Transistor,Fin FET) 2 1-1-2 絕緣層上覆矽(Silicon on Insulator,SOI) 3 1-2 新材料之發展 5 1-1-1 何謂二維材料 8 1-1-2 熱門的二維材料 10 1-3二維材料合成與成長方式 13 1-3-1 一次生長得到二維材料之製作方式 13 機械剝離法 (Mechanical Exfoliation) 13 晶種輔助合成 (Seed Assisted Synthesis) 14 氣相反應 (Gas-phase Reaction) 15 原子層沉積(Atomic layer-deposition) 16 1-3-2二次生長得到二維材料之製作方式 18 熱分解 (Thermolysis) 18 預沉積金屬或氧化物 (Pre-deposited Metal or Metal Oxide) 19 1-4 二維材料在FET方面應用問題 21 1-4-1 使用摻雜通道降低接觸電阻 21 1-4-2 利用改變源/汲極過渡金屬來降低接觸電阻 23 第二章 量測技術及製備設備介紹 26 2-1接觸電阻量測 (Transfer Length Method,TLM) 26 2-3 金氧半場效應電晶體模型 28 2-4光罩設計及元件尺寸說明 31 2-4-1 接觸電阻結構 31 2-4-2 TFT結構 33 2-5製程設備介紹 34 第三章 以機械剝離法取得WS2及MoS2之元件製作與特性量測 44 3-1 元件製作流程 44 3-1-1 機械剝離法流程 44 3-1-2 MoS2之定位 48 3-1-3 厚度判斷 50 3-1-4 機械式剝離法使用之光罩(MoS2,WS2) 51 3-1-5 曝光微影製程 53 3-2 元件結構 56 3-2-1 下閘極 (Back-Gate) FET元件 56 3-3 MoS2及WS2拉曼分析之實驗結果 57 3-4 MoS2及WS2 AFM分析之實驗結果 59 3-5 MoS2及WS2之下閘極(Back-Gate)FET之電性量測結果 60 3-6 MoS2及WS2轉貼技術 64 3-5 結論 66 第四章 以二次成長方式製作摻雜WSe2通道材料與TFT元件特性研究 67 4-1實驗流程 67 4-2電極之金屬或合金鍍膜 72 4-2-1電極金屬 72 4-2-2合成摻雜金屬 74 4-3硒化條件及材料分析 75 4-3-1 拉曼光譜分析 75 4-3-2 TEM分析 84 4-3-3 XPS分析薄膜特性 85 4-3-4結果與討論 86 4-4電性量測 88 4-4-1 接觸電阻量測 88 4-4-2 TFT電性量測 91 4-5結論 95 第五章 結論與未來工作 97 5-1 結論 97 5-2 未來工作 98 參考文獻 99 Publication 103

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