本研究旨在分析於不同閘極寬度、偽閘極陣列數量，以及不同偽閘極間Poly-to-Poly距離的情形下，具矽鍺通道結構N型偽閘極陣列電晶體之應力分佈與性能表現。而經研究後發現，藉由接觸蝕刻停止層結合矽鍺通道結構之應變工程技術可有效提升元件性能。將矽鍺通道因晶格不匹配而產生之應力，與接觸蝕刻停止層之內應力結合，組成多重應力源結構，並藉由三維有限元素分析軟體，模擬分析此結構於N型電晶體內之通道應力分佈。使用3.0 GPa之拉伸應力，做為接觸蝕刻停止層之內應力，並將25 % 做為矽鍺通道之鍺莫耳分率用以模擬分析。分別對偽閘極陣列數量與偽閘極間Poly-to-Poly距離進行調變，結果顯示當電晶體閘極寬度較寬時，單根閘極之載子遷移率比多根偽閘極陣列之情形更為優異，而較短的Poly-to-Poly結構之載子遷移率會比較長的Poly-to-Poly結構更為優異，而最佳之電晶體特性表現將會發生在閘極寬度為100 nm之結構尺寸，約能比傳統電晶體提升40%之效能。

The study focused on analyzing the stress distribution and performance of N-type transistors with silicon germanium channel and dummy gate arrays structure under different gate widths, numbers of dummy gate arrays, and gate pitch (Poly-to-Poly) spacings. Research found by using the strained engineering in contact etch stop layer (CESL) combined with silicon germanium channel structure can be efficiently utilized to enhance the performance of devices. In this research, we have combined the stress from silicon germanium channel lattice mismatch and contact etch stop layer, and simulated the channel stress distribution of this structure in N-type transistors via three-dimensional finite element analysis software. The intrinsic CESL stress considered in this study was tensile (3.0 GPa) (t-CESL). A 25% germanium mole fraction utilized in the Si1-xGex channel was selected to carefully analyze its impact on the Si1-xGex channel. Then we changed the number of dummy gate arrays and the Poly-to-Poly gap between dummy gates. The result shows that with a wider gate width, the carrier mobility of single gate structure is better than the plural dummy gate array, and the carrier mobility of shorter Poly-to-Poly structure is better than longer Poly-to-Poly structure. The best performance of transistors would occur in a 100 nm gate width and enhance 40% compared with the traditional transistors.

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