本研究分析具矽鍺通道結構之N型電晶體，其結構尺寸對於元件之應力分佈與性能表現。該研究證實，藉由接觸蝕刻停止層結合矽鍺應力源之先進應變工程技術，能有效提升元件性能。將矽鍺通道因晶格不匹配而產生之應力，與接觸蝕刻停止層之內應力結合，組成多重應力源結構，並藉由三維有限元素分析軟體，模擬分析此結構於N型電晶體內之通道應力分佈。分別使用1.1 GPa之拉伸應力與-2 GPa之壓縮應力，做為接觸蝕刻停止層之內應力，並將0 %、 22.5 %與 25 % 做為矽鍺通道之鍺莫耳分率用以模擬分析。分析結果指出鍺濃度愈高(大於零)，則晶格不匹配程度愈大，故通道產生之應力愈多。其中，固定鍺濃度為22.5 %且元件閘極寬度為10 m，當改變元件通道長度為0.11、1與10 (m) 時，該元件通道之應力趨勢與電性測量結果相符合。為了觀察三維模擬之表現而改變通道寬度予以分析，結果顯示隨著閘極寬度愈長，三維結果會逐漸收斂至二維結果，可視為一平面應變狀態。
此外，考慮元件佈局圖對於電晶體之應力分佈與性能表現之影響，本研究利用三維有限元素分析，模擬具有內應力之接觸蝕刻停止層與矽鍺層對於延伸閘極結構與通道應力的影響。結果顯示增長延伸閘極之寬度，則延伸閘極彎曲效應增加致使通道應力增加，將使元件性能有所提升，而當延伸寬度大於1 m ，則元件通道應力逐漸趨於飽和狀態。

In this investigation, the effect of structure size of the n-type metal-oxide field-effect transistors (nMOSFET) with SiGe channel structure on the stress distribution and performance of devices was analyzed. This study demonstrated that advanced strained engineering technology in contact etching stop layer (CESL) combined with silicon germanium (Si1-xGex) stressors can be efficiently utilized to enhance the performance of devices. Lattice mismatch stress was induced to establish an Si1-xGex channel integrated with intrinsic stress of CESL, which consists of multiple stressors, to analyze the stress contour of the concerned channel in nMOSFETs by three-dimensional (3D) finite element analysis (FEA). The types of intrinsic CESL stress considered in this study were tensile (1.1 GPa) (t-CESL) and compressive (-2.0 GPa) (c-CESL). Germanium mole fractions, including 0%, 22.5%, and 25%, utilized in the Si1-xGex channel were selected to carefully analyze their impact on the Si1-xGex channel. By contrast, when the foregoing Ge concentration of the SiGe alloy is adjusted (larger than zero), more lattice mismatch is produced. Therefore, the more channel stress generated. Especially, as compared with the electrical properties measured by the 0.11, 1, and 10 (m) of length in channel region, which the channel width is 10 m and Ge mole fraction is 22.5 %. The analytic results show that the stress trends are corresponded with the electrical properties. In order to observe the performance of three-dimensional simulation, we change the channel width to be analyzed. The results showed that when the gate width of the longer, the three-dimensional results will gradually converge to two-dimensional results, that is, a plane strain state.
On the other hand, for the effect of layout of the nMOSFET on the stress distribution and performance of devices was analyzed. In this research, we simulated the stress contour of device induced by CESL and SiGe layer for the effect of protruding gate width through the 3D FEA. The results revealed that as the protruding gate width is increased, more bending effect of protruding gate is increased, the more stress generated that could improve device performance. When protruding gate width is greater than 1 m then the channel stress gradually become saturated.

[1] H. Iwai, “CMOS Technology-Year 2010 and Beyond”, Solid-State Circuits, IEEE, Vol. 34, No. 3, pp.357-366, 1999.
[2] 工研院產業經濟與趨勢研究中心及資策會資訊市場情報中心，2015年台灣重要產業技術發展藍圖I，工研院IEK，2008。
[3] G. E. Moore, “Cramming More Components Onto Integrated Circuits” Electronics, Vol. 38, No.8, pp. 114-117, 1965.
[4] 劉傳璽，陳進來，第三版，半導體物理元件與製程-理論與實務，五南文化出版社，2006。
[5] C. Mahata, M. K. Bera, P. K. Bose, and C. K. maiti, “Charge Trapping Characteristics in High-K Gate Dielectrics on Germanium”, Thin Solid Films 517, Vol. 571, No. 1, pp. 163-166, 2008.
[6] 鄭晃忠，劉傳璽，新世代積體電路製程技術，東華書局，2011。
[7] M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, “A 40 nm Gate Length n-MOSFET”, IEEE Transactions on Electron Devices, Vol. 42, No.10, pp. 1822-1830, 1995.
[8] S. D. Suk, S.-Y. Lee, S.-M. Kim, E.-J. Yoon, M.-S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D.-S. Shin, K.-H. Lee, H. S. Park, J. N. Han, C.J.Park, J.-B. Park, D.-W. Kim, D. Park and B.-I. Ryu, “High Performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : Fabrication on Bulk Si Wafer, Characteristics, and Reliability”, Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp. 717-720, 2005.
[9] K. Rim, J. Welser, J.L. Hoyt, and J.F. Gibbons, “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs”, Electron Devices Meeting, 1995. IEDM '95. International, pp.517-520, 1995.
[10] Viktor Sverdlov, “Strain-Induced Effects in Advanced MOSFETs”, Springer Verlag, 2010.
[11] O. Weber, T. Irisawa, T. Numata, M. Harada, N. Taoka, Y. Yamashita, T. Yamamoto, N. Sugiyama, M. Takenaka and S. Takagi, “Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs”, Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp. 719-722, 2007.
[12] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase and K. Hashimoto, “A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile And High Compressive Silicon Nitride Films”, Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 213–216, 2004.
[13] G. Eneman, E. Simoen, P. Verheyen and K. D. Meyer, “Gate Influence on the Layout Sensitivity of Si1−xGex S/D and Si1−yCy S/D Transistors Including an Analytical Model”, IEEE Transactions on Electron Device, Vol. 55,No. 10, pp. 2703–2711, 2008.
[14] J. S. Lim, S. E. Thompson, and J. G. Fossum, “Comparison of Threshold Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed n-MOSFETs”, IEEE Electron Device Letters, Vol. 25, No. 11, pp. 731–733, 2004.
[15] H.-M. Chen, J.-R. Hwang, Y. Li and F.-L. Yang, “Novel Strained CMOS Devices with STI Stress Buffer Layers”, VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on, pp. 1-2, 2007.
[16] C. C. Lu, J. J. Huang, W. C. Luo, T. H. Hou, and T. F. Lei, “Strained Silicon Technology: Mobility Enhancement and Improved Short Channel Effect Performance by Stress Memorization Technique on nFET Devices”, Journal of The Electrochemical Society, Vol. 157, No. 5, pp. H497-H500, 2010.
[17] S. Takagi, J. L. Hoyt, J. J. Welser and J. F. Gibbons, “Comparative Study of Phonon-Limited Mobility of Two-Dimensional Electrons in Strained and Unstrained Si Metal-Oxide–Semiconductor Field-Effect Transistors”, Journal of Applied Physics, Vol. 80, No. 3, pp. 1567-1577, 1996.
[18] K. Rim, R. Anderson, D. Boyd, F. Cardone, K. Chan, H. Chen, S. Christansen, J. Chu, K. Jenkins, T. Kanarsky, S. Koester, B. H. Lee, K. Lee, V. Mazzeo, A. Mocuta, D. Mocuta, P. M. Mooney, P. Oldiges, J. Ott, P. Ronsheim, R. Roy, A. Steegen, M. Yang, H. Zhu, M. Ieong and H.-S. P. Wong, “Strained Si CMOS (SS CMOS) Technology: Opportunities and Challenges”, Solid-State Electron, Vol. 47, No. 7, pp. 1133-1139, 2003.
[19] K. N. Chiang, C. H. Chang and C. T. Peng, “Local-strain Effects in Si/SiGe/Si Islands on Oxide”, Applied Physics Letters 87, Vol. 87, No. 19, pp. 191901-191901-3, 2005.
[20] S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharaifs, J. Koga, A. Tanabe, N. Hirashita and T. Maeda, “Channel Structure Design, Fabrication and Carrier Transport Properties of Strained-Si/SiGe-on-Insulator (strained-SOI) MOSFETs”, Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International, pp.3.3.1-3.3.4, 2003.
[21] T. Tezuka, N. Sugiyama, and S. Takagi, “Fabrication of Strained Si on an Ultrathin SiGe-on-Insulator Virtual Substrate with a High-Ge Fraction”, Applied Physics Letters, Vol. 79, No. 12, pp. 1798-1800, 2001.
[22] M. T. Currie, T. A. Langdo , G. Taraschi , E. A. Fitzgerald and D. A. Antoniadis, “Carrier Mobilities and Process Stability of Strained Si n- and p-MOSFETs on SiGe Virtual Substrates”, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol. 19, No. 6, pp. 2268-2279, 2001.
[23] H.-M. Chen, J.-R. Hwang, Y. Li and F. L. Yang, “Novel Strained CMOS Devices with STI Stress Buffer Layers”, VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on, pp. 1-2, 2007.
[24] S.E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr and Y. El-Mansy, “A 90-nm Logic Technology Featuring Strained-Silicon”, IEEE Transactions on Electron Device, Vol. 51, No. 11, pp. 1790-1797, 2004.
[25] C.-W. Liu S. Maikop and C.-Y. Yu, “Mobility-Enhancement Technologies”, Circuits and Devices Magazine, IEEE, Vol. 21, No. 3, pp. 21-36, 2005.
[26] M.-C. Wang, H.-C. Yang, W.-S. Liao, H.-Y. Yang, Y.-Y. Hoe, K.-H. Lin and S.-Y. Chen, “CESL Deposition Promoting nip MOSFETs under 45-nm-node Process Fabrication”, Next-Generation Electronics (ISNE), 2010 International Symposium on, pp. 17-20, 2010.
[27] S. Orain, V. Fiori, D. Villanueva, A. Dray and C. Ortolland, “Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors”, IEEE Transactions on Electron Device, Vol. 54, No. 4, pp. 814-821, 2005.
[28] R. C. Hibbeler, “Mechanics of Materials”, Prentice Hall, 2005.
[29] K.Goto, SSatoh, H.Ohta, S.Fukuta, T.Yamamoto, T.Mori, Y.Tagawa, T.Sakuma, TSaiki, Y.Shimamune, A.Katakami, A.Hatada, H.Morioka, Y.Hayami, Shagaki, K.Kawamura, Y.Kim, H.Kokura, N.Tamura, N.Horiguchi, M.Kojima, T.Sugii and K.Hashimoto, “Technology Booster using Strain-Enhancing Laminated SiN (SELS) for 65nm node HP MPUs”, Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 209- 212, 2004.
[30] K.-J. Chui, K.-W. Ang, N. Balasubramanian, M.-F. Li, G. S. Samudra and Y.-C. Yeo, “n-MOSFET With Silicon–Carbon Source/Drain for Enhancement of Carrier Transport”, IEEE Transactions on Electron Devices, Vol. 54, No. 2, pp.249-256, 2007.
[31] W.-S. Liao, Y.-G. Liaw, M.-C. Tang, K.-M. Chen, S.-Y. Huang, C.-Y. Peng, C.-W. Liu, “PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD-SiNx Stressing Layer”, Electron Device Letters, IEEE, Vol. 29, No. 1, pp. 86 – 88, 2008.
[32] Y.-C. Yeo, Q. Lu; T.-J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro and J. Sakai, “Enhanced Performance in Sub-100 nm CMOSFETs using Strained Epitaxial Silicon-Germanium”, Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International, pp. 753 – 756, 2000.
[33] S. Ito, H. Namba, T. Hirata, K. Ando, S. Koyama, N. Ikezawa, T. Suzuki, T. Saitoh and T. Horiuchi, “Effect of Mechanical Stress Induced by Etch-stop Nitride: Impact on Deep-submicron Transistor Performance”, Microelectronics Reliability, Vol. 42, No. 2, pp. 201-209, 2002.
[34] G. Eneman, P. Verheyen, A. D. Keersgieter, M. Jurczak and K. D. Meyer, “Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study”, IEEE Transactions on Electron Devices, Vol. 54, No. 6, pp. 1446-1453, 2007.
[35] Saeed Moaveni, “Finite Element Analysis: Theory and Application with Ansys-3rd Edition”, Prentice Hall, 2007.
[36] 劉晉奇，褚晴暉，有限元素分析與ANSYS的工程應用，滄海書局，2006。
[37] 康淵，陳信吉， ANSYS入門，全華圖書，2007。