隨著B5G和6G的發展，衛星通訊逐漸被視為下一世紀重要發展中的一部分，Ka頻段衛星通訊則在17.7-20.2 GHz和27.5-30 GHz。在相位陣列(Phase Array)架構的射頻接收機中，混頻器(Mixer)和可變增益放大器(Variable Gain Amplifier)為重要的元件。隨著互補式金氧半導體製程(CMOS)的進步，相較於其他製程CMOS具有低成本及低功率消耗等優勢。本論文將使用標準65-nm製程，實現19 GHz高邊帶抑制度單邊帶混頻器與19 GHz可變增益放大器。
第一個電路為19 GHz高邊帶抑制度單邊帶混頻器設計介紹，從混頻器架構、設計參數到模擬量測結果，由單顆混頻器的設計作為基礎，使用被動電阻式環形混頻器架構，能有較好的頻寬特性，且不需要直流功率消耗。再藉由輸入正交訊號，經過I Path混頻器、Q Path混頻器，消除其中一邊頻帶的鏡像訊號，以提高系統靈敏度。該混頻器在LO驅動功率3dBm、閘極偏壓同 V_g 為0.35 V時，轉換增益 -20.3±1.5 dB，在RF頻率13~23 GHz範圍內實現了55.5%的分數頻寬(FBW)，並達到大於30 dBc的寬頻邊帶抑制度。此外，在RF頻率從18.5至20.2 GHz和IF頻率從2.8至5.7 GHz的範圍內，混頻器的邊帶抑制度高於55 dBc。輸出1dB壓縮點(OP1dB)為-15.7 dBm，且整個頻帶的隔離度均優於47 dB，晶片面積為0.885×0.8 mm2，且無直流功率消耗。
第二個電路為19 GHz可變增益放大器，從可變增益放大器架構、設計參數到模擬量測結果，設計上採用Current Steering架構，控制方式為數位控制，本次設計為串接兩級以兼顧雜訊和輸出功率，電晶體類比控制之Current Steering架構來調整增益，使增益可變。除此之外加入Body-Biased架構改善低供應電壓時導致的低可變曾亦範圍問題。低供應電壓和低功耗可變增益放大器。在低供應電壓1V、低功率消耗18mW時，小訊號增益22.38 dB、增益調節範圍9.98 dB，RMS振幅誤差低於0.5 dB，晶片面積為0.825 × 0.55 mm2。

In this thesis, we implemented a 19 GHz single-sideband mixer and a 19 GHz variable gain amplifier with a standard 65-nm 1P9M CMOS process.
For the emerging development beyond current 5G and 6G communication systems, satellite communication is considered as an important candidate for the next generation high speed data link. The SSB mixer is an essential component in the transceiver. Besides, Variable gain amplifiers (VGAs) can adjust the amplitude of each transmitter/receiver chain for reducing the side lobes. The single sideband up-conversion mixer can convert IF frequency with LO frequency to the wanted RF frequency.
The first circuit is a 19 GHz Single-Sideband Mixer. A single sideband (SSB) up-conversion mixer with high sideband suppression (SBS) is presented on 65-nm CMOS technology. Utilizing a high impedance transmission line LO matching network and a 2-stage castle-wall polyphase filter (PPF), the SSB up-conversion mixer achieves high SBS. The measured conversion gain of the mixer is -20.3±1.5 dB from 15 to 31GHz via 3 dBm LO power. The SSB up-conversion mixer achieves broad SBS (>30 dBc) from RF frequency 13 to 23 GHz with the fractional bandwidth (FBW) of 55.5%. In addition, the SBS of the mixer is better than 55 dBc for RF frequencies from 18.5 to 20.2 GHz and IF frequencies from 2.8 to 5.7 GHz. The size of the chip is 885μm × 800μm.
The second circuit is a 19 GHz VGA on 65-nm CMOS process. A body-biased digital current-steering topology is proposed to enlarge the gain control range (GCR) of the VGA under low supply voltage. The proposed VGA achieves a small-signal gain of 22.38 dB at 19 GHz with a 3-dB gain bandwidth from 15.7 to 23.3 GHz. The measured RMS amplitude error is less than 0.5 dB with a GCR of 9.98 dB at 19 GHz. The dc power consumption is 18mW and the chip size is 825μm×550μm.

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