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研究生: 高證穎
論文名稱: 穿隧機制電晶體及交錯型非揮發記憶體選擇器
指導教授: 李敏鴻
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 76
中文關鍵詞: 穿隧機制電晶體Cross-Point 記憶體雙向性二極體
論文種類: 學術論文
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  • 現今工業界正朝著「微小化」的趨勢向前邁進,而奈米技術正是電子元件及電機系統未來繼續發展的基礎,因此從巨觀的元件演變到奈米電子元件是非常關鍵的過程,尤其是現今的45奈米甚至是22奈米世代更顯重要,原因為元件微小化的優點為性能提升及降低消耗功率,也就是說Vdd降低,當scaling到Vt不能再小時勢必也造成Vdd無法再小,問題就是發生在傳統的MOSFET的subthreshold swing最小的物理極限為60mV/dec.,故若能發展新型元件低於60mV/dec,便可解決此問題,穿隧場效電晶體(Tunneling FET)渴望為此問題找到解答,p/i/n操作在reverse bias利用band to band tunneling,可將subthreshold swing降到60mV/dec以下。
    由於記憶體發展的趨勢為高密度、低耗能,而控制電晶體(一般來說是MOSFET)當需要減少元件的大小的時候將面臨問題,平面MOSFET的問題將妨礙記憶體的發展,因此考慮將平面結構發展成三維堆積的結構,而為能適用於雙極性記憶體 (如RRAM) 的使用,則因其寫入及抹除屬不同極性,故需發展雙向型控制單元,類似雙極性載子電晶體 (BJT) 之n/p/n或p/n/p結構,第四章節考慮採用n/p/n接面之雙極性二極體 ( bi-directional diode )期待此選擇器與RRAM記憶體結合,將可提高此二極體的功能性及實用性,可成為未來高密度之3D非揮發性記憶體之控制單元。

    目錄 Publication List ………………………………………………… I 圖目錄 ………………………………………………………… III 表目錄 ………………………………………………………… IX 中文摘要 ……………………………………………………… X 英文摘要 ……………………………………………………… XI 致謝 …………………………………………………………… XII 目錄 …………………………………………………………… XIV 第一章、緒論 1-1 穿隧機制電晶體 ………………………………………… 1 1-2 交錯型非揮發記憶體選擇器 …………………………… 3 第二章、穿隧機制電晶體原理及製作 2-1 前言 ……………………………………………………… 5 2-2 文獻回顧 ………………………………………………… 7 2-3 元件操作原理 …………………………………………… 14 2-4 元件製作流程與設計 …………………………………… 19 第三章 穿隧機制電晶體電性量測 3-1 前言 ……………………………………………………… 25 3-2 C-V量測分析 …………………………………………… 26 3-3 波退火與RTA的比較 ………………………………… 28 3-4 有無Ni dopant segregation的比較 …………………… 32 3-5 有無Ge的比較 ………………………………………… 36 第四章 交錯型非揮發記憶體選擇器開發 4-1 前言 …………………………………………………… 39 4-2 操作原理說明 ………………………………………… 40 4-3 元件製作流程與設計 ………………………………… 41 4-4 實驗電性之量測與分析 ……………………………… 45 4-4-1 元件電性討論 …………………………………… 45 4-4-2 Parasitic Resistance ……………………………… 50 4-4-3 常溫下的穩定性量測 …………………………… 54 4-4-4 升溫下的穩定性量測 …………………………… 60 第五章 結論與未來工作 5-1 結論 …………………………………………………… 66 5-1-1 穿隧機制電晶體 ………………………………… 66 5-1-2 交錯型非揮發記憶體選擇器 …………………… 66 5-2 未來工作 ……………………………………………… 67 參考文獻 …………………………………………………… 70 附錄 ………………………………………………………… 75

    [1]F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, and S. Deleonibus, “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance, ” in IEDM Tech. Dig., pp. 163-166, 2008.
    [2]T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60mV/dec Subthreshold Slope, ” in IEDM Tech. Dig., pp. 947-949, 2008.
    [3]International Technology Roadmap for Semiconductors (ITRS) Roadmap, 2009.
    [4]H.-S. Philip Wang, “Introduction and Overview” in “VLSI Technology Beyond 14 nm Node, ” IEEE IEDM short course, Dec. 4, 2011.
    [5]E. Takeda, H. Matsuoka, Y. Jgura, and S. Asai, “A Band to band Tunneling MOS Device (B2T-MOSFET) – A Kind of “Si Quantum Device”–, ” in IEDM Tech. Dig., pp. 402-405, 1988.
    [6]M. Takayanagi, S. Iwabuchi, T. Kobori, and T. Wada, “A New Band-to-Band Tunneling Model for Accurate Device Simulation of Si MOSFETs, ” in IEDM Tech. Dig., pp. 311-314, 1989.
    [7]K. K. Bhuwalka, J. Schulze, and I. Eisele, “Performance Enhancement of Vertical Tunneling Field-Effect Transistor with SiGe in the δp+ Layer, ”Jap. J. of Appl. Phy., vol. 43, no. 7A, pp. 4073-4078, 2004.
    [8]M. Sterkel, P.-F.Wang, T. Nirschl, B. Fabel, K. K. Bhuwalka, J. Schulze, I. Eisele, D. Schmitt-Landsiede ,and W. Hansch, “Characteristics and Optimization of Vertical and Planar Tunneling-FETs, ” Journal of Physics: Conference Series 10, pp. 15–18, 2005.
    [9]A. I. Khan, C. W. Yeung, C. Hu, and S. Salahuddin, “Ferroelectric Negative Capacitance MOSFET: Capacitance Tuning & Antiferroelectric Operation, ” in IEDM Tech. Dig., pp. 255-258, 2011.
    [10]M. Born, K. K. Bhuwalka, M. Schindler, U. Abelein, M. Schmidt, T. Sulima, and I. Eisele, “Tunnel FET: A CMOS Device for High Temperature Applications, ” in Proc. 25th Int. Conf. Microelectron., 2006, pp. 124-127.
    [11]W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B.-G. Park, “70-nm Impact-Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs), ” in IEDM Tech. Dig., 2005, pp. 955-958.
    [12]K. Joen, W.-Y. Lop, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. King Liu, and C. Hu, “Si Tunnel Transistors with a Novel Silicided Source and 46mV/dec Swing, ” in VLSI Symp. Tech. Dig., 2010, pp. 121-122.
    [13]Q. Huang, Z. Zhan, R. Huang, X. Mao, L. Zhang, Y. Qiu, Y. Wang, “Self-Depleted T-gate Schottky Barrier Tunneling FET with Low Average Subthreshold Slope and High ION/IOFF by Gate Configuration and Barrier Modulation, ” in IEDM Tech. Dig., pp. 382-385, 2011.
    [14]S. M. Sze, Physics of semiconductor devices, 2nd edition, John Wiley & Sons, Inc., 1981.
    [15]J. Moll, “Physics of Semiconductors” McGraw-Hill, New York, p. 253, 1964.
    [16]A. Seabaugh, “Tunnel Field-Effect Transistor – Engineer a Better Switch” in “VLSI Technology Beyond 14 nm Node, ” IEEE IEDM short course, Dec. 4, 2011.
    [17]C. Hu, ICSICT, pp. 16-20 (2008).
    [18]Y.-J. Lee, F.-K. Hsueh, S.-C. Huang, J. M. Kowalski, J. E. Kowalski, Alex T. Y. Cheng, A. Koo, G.-L. Luo, and C.-Y. Wu, “A Low-Temperature Microwave Anneal Process for Boron-Doped Ultrathin Ge Epilayer on Si Substrate, ” IEEE Electron Device Lett., vol. 30, no. 2, pp. 123-125, February, 2009.
    [19]F.-K. Hsueh, Y.-J. Lee, K.-L. Lin, M. I. Current, C.-Y. Wu, and T.-S. Chao, “Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing, ” IEEE Transactions On Electron Devices, VOL. 58, NO. 7, pp. 2088-2093, JULY 2011
    [20]H.Tanaka, M.Kido, K.Yahashi, M.Oomura, R.Katsumata, M.Kito, Y.Fukuzumi, M.Sato, Y.Nagata, Y.Matsuoka, Y.Iwata, H.Aochi and A.Nitayama, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory” ,in VLSI. Tech. Dig., pp. 14-15,2007.
    [21]Katsumata, R.; Kito, M.; Fukuzumi, Y.; Kido, M.; Tanaka, H.; Komori, Y.; Ishiduki, M.; Matsunami, J.; Fujiwara, T.; Nagata, Y.; Li Zhang; Iwata, Y.; Kirisawa, R.; Aochi, H.; Nitayama, A., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices” , in VLSI. Tech. Dig., pp. 136 – 137,2009.
    [22]Jaehoon Jang, Han-Soo Kim, Wonseok Cho, Hoosung Cho, Jinho Kim, Sun Il Shim, Younggoan Jang, Jae-Hun Jeong, Byoung-Keun Son, Dong Woo Kim, Kihyun Kim, Jae-Joo Shim, Jin Soo Lim, Kyoung-Hoon Kim, Su Youn Yi, Ju-Young Lim, Dewill Chung, Hui-Chang Moon, Sungmin Hwang,Jong-Wook Lee, Yong-Hoon Son, U-In Chung and Won-Seong Lee, “Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory” ,in VLSI. Tech. Dig., pp. 192 – 193, 2009.
    [23]Jiyoung Kim, Augustin J. Hong, Sung Min Kim, Emil B. Song, Jeung Hun Park, Jeonghee Han, Siyoung Choi, Deahyun Jang, Joo-Tae Moon, and Kang L .Wang, “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)” ,in VLSI. tech. Dig., pp.186-187,2009
    [24]F. Pellizzer, et al., “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications ,”Symp. VLSI Tech. Digest of Tech Papers, pp. 122-123, 2006.
    [25]F. Pellizzer, et al., “Novel Trench Phase-Change Memory Cell for Embedded and Stand-Alone Non-Volatile Memory Applications,” Symp. VLSI Tech. Digest of Tech Papers, pp. 18-19, 2004.
    [26]G. Atwood, et al., “Current Status of Chalcogenide Phase Change Memory,” DRC, pp. 29-33, 2005.
    [27]H.-S. Philip Wong, et al., “Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies,” Electron Devices, pp. 29-33, 2005
    [28]C. Amsinck, et al., “Translating the Integration Challenges to Molecular Device Requirements – Analysis of Scaling Constraints in Molecular Random Access Memories,”Nanotech ,vol.3, pp. 61-64, 2004

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