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研究生: 高證穎
論文名稱: 穿隧機制電晶體及交錯型非揮發記憶體選擇器
指導教授: 李敏鴻
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 76
中文關鍵詞: 穿隧機制電晶體Cross-Point 記憶體雙向性二極體
論文種類: 學術論文
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  • 現今工業界正朝著「微小化」的趨勢向前邁進,而奈米技術正是電子元件及電機系統未來繼續發展的基礎,因此從巨觀的元件演變到奈米電子元件是非常關鍵的過程,尤其是現今的45奈米甚至是22奈米世代更顯重要,原因為元件微小化的優點為性能提升及降低消耗功率,也就是說Vdd降低,當scaling到Vt不能再小時勢必也造成Vdd無法再小,問題就是發生在傳統的MOSFET的subthreshold swing最小的物理極限為60mV/dec.,故若能發展新型元件低於60mV/dec,便可解決此問題,穿隧場效電晶體(Tunneling FET)渴望為此問題找到解答,p/i/n操作在reverse bias利用band to band tunneling,可將subthreshold swing降到60mV/dec以下。
    由於記憶體發展的趨勢為高密度、低耗能,而控制電晶體(一般來說是MOSFET)當需要減少元件的大小的時候將面臨問題,平面MOSFET的問題將妨礙記憶體的發展,因此考慮將平面結構發展成三維堆積的結構,而為能適用於雙極性記憶體 (如RRAM) 的使用,則因其寫入及抹除屬不同極性,故需發展雙向型控制單元,類似雙極性載子電晶體 (BJT) 之n/p/n或p/n/p結構,第四章節考慮採用n/p/n接面之雙極性二極體 ( bi-directional diode )期待此選擇器與RRAM記憶體結合,將可提高此二極體的功能性及實用性,可成為未來高密度之3D非揮發性記憶體之控制單元。

    目錄 Publication List ………………………………………………… I 圖目錄 ………………………………………………………… III 表目錄 ………………………………………………………… IX 中文摘要 ……………………………………………………… X 英文摘要 ……………………………………………………… XI 致謝 …………………………………………………………… XII 目錄 …………………………………………………………… XIV 第一章、緒論 1-1 穿隧機制電晶體 ………………………………………… 1 1-2 交錯型非揮發記憶體選擇器 …………………………… 3 第二章、穿隧機制電晶體原理及製作 2-1 前言 ……………………………………………………… 5 2-2 文獻回顧 ………………………………………………… 7 2-3 元件操作原理 …………………………………………… 14 2-4 元件製作流程與設計 …………………………………… 19 第三章 穿隧機制電晶體電性量測 3-1 前言 ……………………………………………………… 25 3-2 C-V量測分析 …………………………………………… 26 3-3 波退火與RTA的比較 ………………………………… 28 3-4 有無Ni dopant segregation的比較 …………………… 32 3-5 有無Ge的比較 ………………………………………… 36 第四章 交錯型非揮發記憶體選擇器開發 4-1 前言 …………………………………………………… 39 4-2 操作原理說明 ………………………………………… 40 4-3 元件製作流程與設計 ………………………………… 41 4-4 實驗電性之量測與分析 ……………………………… 45 4-4-1 元件電性討論 …………………………………… 45 4-4-2 Parasitic Resistance ……………………………… 50 4-4-3 常溫下的穩定性量測 …………………………… 54 4-4-4 升溫下的穩定性量測 …………………………… 60 第五章 結論與未來工作 5-1 結論 …………………………………………………… 66 5-1-1 穿隧機制電晶體 ………………………………… 66 5-1-2 交錯型非揮發記憶體選擇器 …………………… 66 5-2 未來工作 ……………………………………………… 67 參考文獻 …………………………………………………… 70 附錄 ………………………………………………………… 75

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