現今的科技日新月異，在類比數位轉換器(Analog-to-Digital Converter，ADC)晶片的音頻應用(audio-band application)中不但對於高解析度有所要求，對於低功率的需求也逐漸受到重視。在這項應用中以三角積分調變器(Delta-Sigma Modulator，ΔΣM)為主，因其解析度最高，但是相對上功率消耗也是最高的，如何在不影響電路效能的情形下最佳化三角積分調變器的功率消耗是本篇論文的核心目標。
本論文中，提出了兩個可以在不影響電路效能的情形下最佳化三角積分調變器的功率消耗的電路，分別為一個使用NS SAR 量化器之多重迴路三角積分調變器和利用一顆反相器基底積分器實現的一個二階雙路徑三角積分調變器，皆以UMC 180nm CMOS製程實現，供應電壓均使用1.4 V。前者的核心電路佈局模擬SNDR值為88.78 dB，總功率消耗為128 uW，後者的核心電路佈局模擬SNDR值為84.75 dB，總功率消耗為48 uW。
兩者的共通點是皆採用了逐次逼近式類比數位轉換器(Successive Approximation Register ADC，SAR ADC)做為量化器(Quantizer)，以及雜訊移頻(Noise-Shaping，NS)技術。前者主要透過多級雜訊移頻(Multi-Stage Noise-Shaping，MASH)架構和數位濾波器(Digital Filter)以達到消除多餘雜訊的效果，後者主要藉由一個反相器基底積分器搭配雙路徑架構來實現一個二階雙路徑之反相器基底積分器，對電路元件的利用效率最佳化。

In the realm of rapidly evolving technology, there is an increasing emphasis on both high resolution and low power consumption in audio-band applications of Analog-to-Digital Converter (ADC) chips. Delta-Sigma Modulators (ΔΣMs) are commonly employed in these applications for their exceptional resolution; however, they also exhibit a substantial power consumption. The core objective of this paper is to optimize the power consumption of ΔΣMs without compromising the circuit performance.
In this paper, two circuits are proposed to optimize the power consumption of ΔΣMs while maintaining the performance. The first proposed circuit is a noise-shaping SAR-assisted MASH ΔΣM and the second proposed circuit is a second-order pseudo-two-path inverter-based ΔΣM. Both circuits are implemented using the UMC 180nm CMOS process with the supply voltage of 1.4V. A simulated SNDR value of 88.78 dB with a total power consumption of 128 uW is achieved by the first circuit, while the second circuit achieves a simulated SNDR value of 84.75 dB with a total power consumption of 48 uW.
To achieve the optimization of power consumption, the employment of a quantizer in the form of a Successive Approximation Register ADC (SAR ADC) and the utilization of Noise-Shaping (NS) techniques are enabled by the proposed circuits. A Multi-Stage Noise-Shaping (MASH) architecture and digital filters are implemented by the first circuit, effectively eliminating excess noise. An inverter-based integrator with a pseudo-two-path structure is utilized by the second circuit to realize a second-order ΔΣM with only one integrator and maximize the efficiency of circuit components.

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