簡易檢索 / 詳目顯示

回結果列表
研究生： 林翰江
Han-Chiang Lin
論文名稱： 高效能逐次逼近式類比數位轉換器的設計與實現
Design and Implementation of Energy Efficient Successive-Approximation Analog-to-Digital Converters
指導教授： 郭建宏
Kuo, Chien-Hung
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 中文
論文頁數： 75
中文關鍵詞： 類比數位轉換器 、逐次逼近暫存器 、電容式數位類比轉換電路 、品質因數FOM
英文關鍵詞： Analog-to-digital converter, successive approximation register, capacitive DAC array, figure of merit (FOM)
論文種類： 學術論文
相關次數： 點閱：320  下載：24 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 積體電路設計在製程技術的進步之下，製程技術提升可以大量降低電路佈局的面積，也使得電路運作的電壓因而縮小，使得低功率與高效能的電路設計不斷推出。可攜式的電子產品在消費市場上越來越多，輕薄短小以及電池的長時效性要求，漸漸成為電路設計之主流；尤其是應用在人體或生物上的植入性醫學晶片，為了能達到長時間使用不更換的目標，低功率在電路的設計上，更顯得重要。在眾多的類比數位轉換器中，逐次逼近式類比數位轉換器(successive approximation register analog-to-digital converter, SAR ADC)最適合應用在低功率的系統中，此架構僅需一顆比較器即可完成資料轉換，這項優點可大幅地縮減資料轉換所消耗的功耗。
    在本論文中，提出兩種架構分別為，二次浮動開關電容式SAR ADC和分裂式浮動開關SAR ADC架構。在二次浮動開關電容式SAR ADC此架構中，DAC部分的功率消耗相較於傳統切換技術之DAC架構，所提出方法可有效的節省97.57%的平均能量，採用TSMC 0.18-μm 1P6M的標準製程完成，在奈式取樣頻寬的規格下，分別可達到的品質因數FOM值為105.86-fJ/conversion-step。另外，在分裂式浮動開關之SAR ADC架構，在電容佈局方面，相較於傳統DAC架構可節省96.875%的電容佈局面積，採用TSMC 0.18-μm 1P6M的標準製程完成，分別可達到的品質因數FOM值為29.47-fJ/conversion-step。

    With the development of modern CMOS fabrication, the advancement of fabrication processing is capable of reducing the area of integrated circuit layout and lowering the voltage during circuit operation, producing a constant stream of low-power and high-performance circuits. With the raising number of portable electronic devices, portability as well as battery endurance have become the mainstream of chips performance. Especially in the application of human or biological implantation, the importance of low-power circuit design become much greater. Among different type of analog-to-digital converters (ADC), successive approximation register (SAR) is the most appropriate for low-power designs. Becouse it only takes one comparator to complete the whole sampling data during each conversion phase, which significantly reduces the power dissipation.

    In this thesis, there are two schemes：(1) double partial FCS scheme based single-ended SAR ADC, (2) the partial FCS scheme based differential SAR ADC .Applying double partial FCS scheme based single-ended SAR ADC can efficiently reduce 97.57% of average switching energy compared to the conventional DAC approach. Constructed by TSMC 0.18-μm 1P6M process technology, the presented SAR ADC can achieve 105.86-fJ/conversion-step figure of merit (FOM) in the Nyquist bandwidth. In addition, applying the partial FCS scheme based differential SAR ADC can efficiently reduce 96.875% of Capacitor layout area compared to the conventional DAC approach. Constructed by TSMC 0.18-μm 1P6M process technology, the presented SAR ADC can achieve 29.47-fJ/conversion-step figure of merit (FOM).

    中文摘要 .........................................................................................................................I 英文摘要 ........................................................................................................................II 誌　　謝 .......................................................................................................................IV 目　　錄 ........................................................................................................................V 圖 目 錄 ......................................................................................................................IX 表 目 錄 .....................................................................................................................XII 第一章　緒論.................................................................................................................1 　　1.1　研究背景與動機............................................................................................1 　　1.2　混合信號系統概述........................................................................................2 　　1.3　論文架構與研究方法....................................................................................3 第二章　類比數位轉換器概論.....................................................................................4 　　2.1　前言................................................................................................................4 　　2.2　效能指標........................................................................................................5 　 2.2.1　信號雜訊比...........................................................................................5 　　　 2.2.2　信號雜訊失真比...................................................................................6 　　　 2.2.3　動態範圍...............................................................................................6 　　　 2.2.4　無雜散動態範圍...................................................................................7 　　　 2.2.5　非線性誤差...........................................................................................7 　　　 2.2.6　品質因數...............................................................................................7 2.3　量化器與量化誤差........................................................................................8 　　　2.3.1　二位元量化器.........................................................................................8 　　　2.3.2　多位元量化器.........................................................................................9 　　　　1. Mid-rise量化器...........................................................................................9 　　　　2. Mid-tread量化器...................................................................................... 10 　　　　3. 多位元量化器的非理想特性.................................................................. 11 　　2.4量化誤差的產生.............................................................................................. 12 　　2.5類比數位轉換器各式架構……...................................................................... 13 　　　2.5.1　逐次逼近式類比數位轉換器............................................................... 13 　　　2.5.2　二位元搜尋法....................................................................................... 14 第三章　SAR ADC之電路元件................................................................................. 16 　　3.1　取樣保持電路.............................................................................................. 16 　　　3.1.1　開關電路............................................................................................... 16 　　　3.1.2　NMOS開關與PMOS開關................................................................... 16 　　　3.1.3　傳輸閘開關........................................................................................... 17 　　3.2　低臨界電壓技術.......................................................................................... 18 　　　3.2.1　時脈倍壓電路....................................................................................... 18 　　3.3　靴帶式開關.................................................................................................. 19 　　　3.3.1　以靴帶式開關實現之取樣保持電路................................................... 20 　　3.4　比較器電路.................................................................................................. 23 　　　3.4.1　動態比較器........................................................................................... 24 　　3.5　逐次逼近暫存器.......................................................................................... 26 　　　3.5.1　Non-redundant SAR工作程序............................................................. 27 　　　3.5.2　Non-redundant SAR電路實現............................................................. 28 　　　3.5.3　單相位時序正反器............................................................................... 29 　　3.6　數位類比轉換器.......................................................................................... 30 　　　3.6.1　電阻式數位類比轉換器....................................................................... 31 　　　3.6.2　電流式數位類比轉換器....................................................................... 33 　　　3.6.3　電容式數位類比轉換器....................................................................... 33 　　3.7　時脈產生器.................................................................................................. 34 第四章　高效能SAR ADC的設計............................................................................ 36 　　4.1　切換電容能量損耗...................................................................................... 36 　　4.2　傳統SAR ADC架構................................................................................... 36 　　　4.2.1　取樣保持狀態之能量分析................................................................... 37 　　　4.2.2　電荷重新分佈之能量分析................................................................... 39 　　4.3　傳統SAR ADC架構能量損耗.................................................................... 43 　　4.4　浮動開關電容式SAR ADC........................................................................ 44 　　4.5　二次浮動開關電容式SAR ADC架構........................................................ 46 　　　4.5.1　二次浮動開關電容式SAR ADC架構能量損耗................................. 49 　　4.6　分裂式浮動開關之SAR ADC架構........................................................... 49 第五章　SAR ADC電路實現..................................................................................... 53 　　5.1　二次浮動開關電容式SAR ADC電路設計與模擬................................... 53 　　 5.1.1　電路佈局與實現................................................................................... 54 5.1.2　晶片量測環境....................................................................................... 55 　　 5.1.3　量測結果............................................................................................... 60 　 5.2　分裂式浮動開關之SAR ADC電路設計與模擬....................................... 62 　　 5.2.1　電路佈局與實現................................................................................... 62 　　 5.2.2　量測結果............................................................................................... 64 　　5.3　總結.............................................................................................................. 66 第六章　總結與未來展望........................................................................................... 67 　　6.1　總結.............................................................................................................. 67 　　6.2　未來展望...................................................................................................... 68 參　考　文　獻........................................................................................................... 70 作　者　簡　歷....................................................................................................... 74 學　術　成　就....................................................................................................... 75

    [1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Companies, Inc., 2002.
    [2] D. A. Johns and K. Martin, Analog CMOS Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
    [3] K.-L. Lin, A. Kemna, and B. J. Hosticka, Modular low-power, high-speed CMOS analog-to-digital converter for embedded systems, Kluwer Academic Publishers, 2003.
    [4] R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Second Edition, John Wiley & Sons, Inc., 2008.
    [5] J. McCreary and P. R. Gray, “A high-speed, all-MOS successive-approximation weighted capacitor A/D conversion technique,” IEEE Int. Solid-State Circuits Conf., Feb. 1975, pp. 38–39.
    [6] J. Sauerbery, T. Tille, D. S. Landsiedel, and R. Thews, “A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1662–1669, Dec. 2002.
    [7] G.-C. Ahn, D.-Y. Chang, M. E. Brown, N. Ozaki, H. Youra, K. Hamashita, K. Takasuka, G. C. Temes, and U.-K. Moon, “A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2398–2407, Dec. 2005.
    [8] J. Shen and P. Kinget, “A 0.5-V 8-bit 10-Msps pipelined ADC in 90-nm CMOS,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 202–203.
    [9] M. Waltari and K. A. I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE J. Solid-State Circuits, vol. 36, no. 1, Jan. 2001.
    [10] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1-μW successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261–1265, Jul. 2003.
    [11] H.-C. Hong and G.-M. Lee, “A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161–2168, Oct. 2007.
    [12] C.-H. Kuo and C.-E. Hsieh, “A high energy-efficiency SAR ADC based on partial floating capacitor switching technique,” IEEE Eur. Solid-State Circuits Conf., Sep. 2011, pp. 475–478.
    [13] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” IEEE Int. Symp. Circuits Syst., May 2005, pp. 184–187.
    [14] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007.
    [15] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500-KS/s low power SAR ADC for bio-medical applications,” IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 228–231.
    [16] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010.
    [17] V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, no. 9, pp. 620–621, Apr. 2010.
    [18] T. Anand, V. Chaturvedi, and B. Amrutur, “Energy efficient asymmetric binary search switching technique for SAR ADC,” Electron. Lett., vol. 46, no. 22, pp. 1487–1488, Oct. 2010.
    [19] Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111–1121, Jun. 2010.
    [20] C.-H. Kuo and C.-E. Hsieh, “Floating capacitor switching SAR ADC,” Electron. Lett., vol. 47, no. 13, pp. 742–743, Jun. 2011.
    [21] M. Dessouky and A. Kaiser, “Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 349–355, Mar. 2001.
    [22] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched op amp circuits,” Electron. Lett., vol. 35, no. 1, pp. 8–10, Jan. 1999.
    [23] H. T. Russell and JR., “An improved successive-approximation register design for use in A/D converters,” IEEE Trans. Circuits Syst., vol. 25, no. 7, pp. 550–554, Jul. 1978.
    [24] A. Rossi and G. Fucili, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, pp. 1055–1057, Jun. 1996.
    [25] J. Yuan and C. Svensson, “New TSPC latches and flipflops minimizing delay and power,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1996, pp. 160–161.
    [26] M. Elzakker, E. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC consuming 1.9-μW at 1-MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007–1015, May 2010.
    [27] A. Nikoozadeh and B. Murmann, “An analysis of latch comparator offset due to load capacitor mismatch,” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 12, pp. 1398–1402, Dec. 2006.
    [28] J. He, S. Zhan, D. Chen, and R. L. Geiger, “Analyses of static and dynamic random offset voltages in dynamic comparators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp. 911–919, Jul. 2009.
    [29] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, 1999.
    [30] N. Verma and A. P. Chandrakasan, “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1196–1205, Jun. 2007.
    [31] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB 1-V 3.8-μW 100-kS/s SAR ADC with time-domain comparator,” IEEE Int. Solid State Circuits Conf., Feb. 2008, pp. 245–247.
    [32] W.-Y. Pang, C.-S. Wang, Y.-K. Chang, N.-K. Chou, and C.-K. Wang, “A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications,” IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 149–152.
    [33] G. Yin, U-F. Chio, H.-G. Wei, S.-W. Sin, S.-P. U, R. P. Martins, and Z. Wang, “An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications,” IEEE Int. Conf. Electron. Circuits Syst., Dec. 2010, pp. 878–881.
    [34] J.-H. Cheong, K.-L. Chan, P. B. Khannur, K.-T. Tiew, and M. Je, “A 400-nW 19.5-fJ/conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18-μm CMOS,” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 58, no. 7, pp. 407–411, Jul. 2011.

    下載圖示
    QR CODE