隨著科技演進元件微縮已面臨瓶頸，各領域的專家嘗試透過不同的方式如:結構堆疊、改變通道或是介電層材料等，設法利用現有的製程來解決線寬微縮所遇到的問題。其中利用鐵電材料當作介電層的元件在近年來相當受到研究人員的關注，因為鐵電材料為高K材料又同時擁有雙穩態的特性有助於改善現行元件。
本論文使用ALD (Atomic layer deposition) supercycle方式成長鉿基氧化物材料，故具有超薄和保角特性(Conformal)之優點。而此材料和FET整合也已經被廣泛的研究已利用於當前CMOS架構。本論文展示雙層Ω型FeFET具有電晶體（1T）存儲架構的可靠性應用在環繞式電晶體，(GAA-FET)上。根據實驗結果memory window (MW)=0.9V，及電流開關比可以達到104等優勢，有機會成為未來世代鰭式電晶體與應用在記憶體計算上的目標。透過搭配TiO2氧化層來降低退火溫度，同時設法提高電容有效電荷儲存量，探討TiO2在不同堆疊位置上之不同特性，研究在鐵電電晶體和鐵電電容上的特性。並研究多層堆疊技術，搭配不同濃度Hafnium-Zirconium-Oxide (HZO)與層數，達成在有效面積上提高鐵電效應於記憶體，整合上述技術期望能應用在現今記憶體的操作上。

The scaling of transistors has faced a bottleneck, with the advance of science and technology. Some approaches have been proposed to address the problem, such as stacked structure, changing the channel or dielectric layer materials, etc. Due to bi-stable state nature feature and high-k properties, ferroelectric materials as a dielectric layer integrated with current CMOS processes have been extensively investigated in recent year.
The ALD (atomic layer deposition) supercycle approach is employed for Hafnium-Zirconium-Oxide (HZO) deposition, which has the advantages of ultrathin ability and conformal deposition for GAA-FETs. The double layer Ω-type HZO FET is demonstrated for one-transistor (1T) memory architecture . The memory window (MW) is 0.9V with Ion/Ioff ratio over 104. Besides, owing to lower of annealing temperature and the charge storage enhancement, TiO2 integrated with HZO on MFM capacitor and FeFET application worth further research. Finally, the laminated Hafnium-based oxide FeFET stack structure is studied for multi-level states and high-density storage. This work may pave the way for emerging memory applications.

[1] T. Boescke, J. Heitmann, U. Schroder, “Integrated circuit with dielectric layer, ” US 7,709,359 B2, 2010 (Filing date 2007-09-05).
[2] T. Ali, P. Polakowski, T. Büttner, T. Kämpfe, M. Rudolph, B. Pätzold, R. Hoffmann, M. Czernohorsky, K. Kühnel, P.Steinke, L. M. Eng, and K. Seidel, “Principles and Challenges for Binary Oxide Based Ferroelectric Memory FeFET, ” in International Memory Workshop, P3. May 2019.
[3] T. Ali, P. Polakowski, K. Kühnel, M. Czernohorsky, T. Kämpfe, M. Rudolph, B. Pätzold, D. Lehninger, F. Müller, R. Olivo, M. Lederer, R. Hoffmann, P. Steinke, K. Zimmermann, U. Mühle, K. Seidel, and J. Müller, “A Multilevel FeFET Memory Device based on Laminated HSO and HZO Ferroelectric Layers for High-Density Storage, ” in IEDM Tech. Dig., Dec. 2019, pp. 665-668.
[4] M. Noriyuki , “Electric-feld-controlled interface dipole modulation for Si-based memory devices, ” Scientific Reports, vol.8, May 2018, Art. no. 8486.
[5] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, T.-J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned double-gate MOSFET scalable beyond 20 nm, ” IEEE Trans. on Electron Device, vol. 47, no.12, pp. 2320-2325, Dec. 2000.
[6] N. Loubet, T. Hook, P. Montanini, C. W. Yeung, S. Kanakasabapathy, M. Guillorn, T. Yamashita, J. Zhang, X. Miao, J. Wang, A. Young, R. Chao, M. Kang, Z. Liu, S. Fan, B. Hamieh, S. Sieg, Y. Mignot, W. Xu, S. C. Seo, J. Yoo, S. Mochizuki, M. Sankarapandian, O. Kwon, A. Carr, A. Greene, Y. Park, J. Frougier, R. Galatage, R. Bao, J. Shearer, R. Conti, H. Song, D. Lee, D. Kong, Y. Xu, A. Arceo, Z. Bi, P. Xu, R. Muthinti, J. Li, R. Wong, D. Brown, P. Oldiges, R. Robison, J. Arnold, N. Felix, S. Skordas, J. Gaudiello, T. Standaert, H. Jagannathan, D. Corliss, M.-H. Na, A. Knorr, T. Wu, D. Gupta, S. Lian, R. Divakaruni, T. Gow, C. Labelle, S. Lee, V. Paruchuri, H. Bu, and M. Khare, “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, ” in VLSI Technology Symp., 2012, pp. 230-231.
[7] R. Loo, A. Y. Hikavyy, L. Witters, A. Schulze, H. Arimura, D. Cott, J. Mitard, C. Porret, H. Mertens, P. Ryan, J. Wall, K. Matney, M. Wormington, P. Favia, O. Richard, H. Bender, A. Thean, N. Horiguchi, D. Mocuta and N. Collaert, “Processing Technologies for Advanced Ge Devices, ” ECS J. Solid State Sci. Technol., vol. 6, no. 1, pp. 14-20, 2017.
[8] T. P.-C. Juan, C.-Y. Chang, and J. Y.-M. Lee, “A New Metal –Ferroelectric (PbZr0.53Ti0.47O3) – Insulator (Dy2O3) Semiconductor (MFIS) FET for Nonvolatile Memory Applications, ” IEEE Electron Device Lett., vol. 27, no. 4, pp. 217-220, May 2006.
[9] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in Hafnium Oxide: CMOS compatible Ferroelectric Field Effect Transistors, ” in IEDM Tech. Dig., Dec. 2011, pp. 547-550.
[10] J. Müller, T.S. Böscke, S. Müller, E. Yurchuk, P. Polakowski, J. Paul, D. Martin, T. Schenk, K. Khullar, A. Kersch, W. Weinreich, S. Riedel, K. Seidel, A. Kumar, T.M. Arruda, S.V. Kalinin, T. Schlösser, R. Boschke, R. van Bentum, U. Schröder, and T. Mikolajick, “Ferroelectric Hafnium Oxide: A CMOS-compatible and highly scalable approach to future ferroelectric memories, ” in IEDM Tech. Dig., Dec. 2013, pp. 280-283.
[11] M. H. Lee, P.-G. Chen, S.-T. Fan, Y.-C. Chou, C.-Y. Kuo, C.-H. Tang, H.-H. Chen, S.-S. Gu, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, C.-Y. Liao, K.-T. Chen, S. T. Chang, M.-H. Liao, K.-S. Li, and C. W. Liu, “Ferroelectric Al:HfO2 Negative Capacitance FETs, ” in IEDM Tech. Dig., Dec. 2017, pp. 565-568.
[12] M. H. Park, H. J. Kim, Y. J. Kim, T. Moon, K. D. Kim, and C. S. Hwang, “Toward a multifunctional monolithic device based on pyroelectricity and the electrocaloric effect of thin antiferroelectric HfXZr1−XO2 films, ” Nano Energy, vol. 12, pp. 131-140, Mar. 2015.
[13] R. Eskandari, X. Zhang, and L. M. Malkinski, “Polarization-dependent photovoltaic effect in ferroelectric-semiconductor system, ” Applied Physics Letters, vol. 110,2017, Art. on. 21105.
[14] M. H. Lee, K.-T. Chen, C.-Y. Liao, G.-Y. Siang, C. Lo, H.-Y. Chen, Y.-J. Tseng, C.-Y. Chueh, C. Chang, Y.-Y. Lin, Y.-J. Yang, F.-C. Hsieh, S. T. Chang, M.-H. Liao, K.-S. Li, and C. W. Liu, “Bi-directional Sub-60mV/dec, Hysteresis-Free, Reducing Onset Voltage and High Speed Response of Ferroelectric-AntiFerroelectric Hf0.25Zr0.75O2 Negative Capacitance FETs, ” in IEDM Tech. Dig., Dec. 2019, pp. 566-569.
[15] K. S. Li, P.-G. Chen, T. Y. Lai, C. H. Lin, C.-C. Cheng, C. C. Chen, M.-H. Liao, M. H. Lee, M. C. Chen, J. M. Sheih, W. K. Yeh, F. L. Yang, S. Salahuddin, C. Hu, “Sub-60mV-Swing Negative-Capacitance FinFET without Hysteresis, ” in IEDM Tech. Dig., Dec. 2015, pp. 630-623.
[16] Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J.Liu, J.Shi, H.J. Kim, R. Sporer, C. Serrao, A.Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, and S. Banna, “14nm Ferroelectric FinFET Technology with Steep Subthreshold Slope for Ultra Low Power Applications, ” in IEDM Tech. Dig., Dec. 2017, pp. 357-360.
[17] W. Chung, M. Si, and P. D. Ye, “Hysteresis-free Negative Capacitance Germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec, ” in IEDM Tech. Dig., Dec. 2017, pp. 365-368.
[18] H. Zhou, D. Kwon, A. B. Sachid, Y. Liao, K. Chatterjee, A. J. Tan, A. K. Yadav, C. Hu, and S. Salahuddin, “Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect, ” in VLSI Technology Symp., Jun. 2018, pp. 53-54.
[19] W. Chung, M. Si, P. R. Shrestha, Jason P. Campbell, Kin P. Cheung and P. D. Ye, “First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric Nanowire FETs, ” in VLSI Technology Symp., Jun. 2018, pp. 89-90.
[20] M. H. Lee, K.-T. Chen, C.-Y. Liao, S.-S. Gu, G.-Y. Siang, Y.-C. Chou, H.-Y. Chen, J. Le, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, P.-G. Chen, M. Tang, Y.-D. Lin, H.-Y. Lee, K.-S. Li, and C. W. Liu, “Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs, ” in IEDM Tech. Dig., Dec. 2018, pp. 735-738.
[21] 柯志忠、林秀芬、蕭健男“原子層沉積系統設計概念與應用”儀器科技中心,科儀新知第二十九卷第一期 96.8
[22] K.-T. Chen, H.-Y. Chen, C.-Y. Liao, G.-Y. Siang, J. Le, M.-H. Liao, K.-S. Li, S. T. Chang, and M. H. Lee, “Non-Volatile Ferroelectric FETs using 5-nm Hf0.5Zr0.5O2 with High Data Retention and Read Endurance for 1T Memory Applications, ” IEEE Electron Device Letter, vol. 40, no. 3, pp. 399-402, Jan. 2019.
[23] T.P. Ma, and J.-P. Han, “Why is nonvolatile ferroelectric memory field-effect transistor still elusive?, ” IEEE Electron Device Letter., vol. 23, no. 7, pp. 386-388, Jul. 2002.
[24] M. H. Lee, Y.-T. Wei, C. Liu, J.-J. Huang, M. Tang, Y.-L. Chueh, K.-Y. Chu, M.-J. Chen, H.-Y. Lee, Y.-S. Chen, L.-H. Lee, and M.-J. Tsai, “Ferroelectricity of HfZrO2 in Energy Landscape with Surface Potential Gain for Low-Power Steep-Slope Transistors, ” IEEE Journal of the Electron Devices Society, vol. 3, no. 4, pp. 377-381, 2015.
[25] M. H. Lee, Y.-T. Wei, K. Y. Chu, J. J. Huang, C. W. Chen, C. C. Cheng, M. J. Chen, H. Y. Lee, Y. S. Chen, L. H. Lee, and M. J. Tsai, “Steep Slope and Near Non-Hysteresis of FETs With Antiferroelectric-Like HfZrO for Low-Power Electronics, ” IEEE Electron Device Letter, vol. 36, no. 4, pp. 294-296, Feb, 2015.
[26] S. L. Miller, R. D. Nasby, J. R. Schwank, M. S. Rodgers, and P. V. Dressendorfer, “Device modeling of ferroelectric capacitors, ” Journal of Applied Physics, vol. 68, pp. 6463-6471, 1990.
[27] S. L. Miller, and P. J. McWhorter, “Physics of the ferroelectric nonvolatile memory field effect transistor, ” Journal of Applied Physics, vol. 72, pp. 5999-6010, 1992.
[28] M. Kobayashi, Y. Tagawa, F. Mo, T. Saraya, and T. Hiramoto, “Ferroelectric HfO2 Tunnel Junction Memory With High TER and Multi-Level Operation Featuring Metal Replacement Process, ” Journal of Electron Devices Society, vol. 7, pp. 134-139, 2019.
[29] H. H. Huang, T. Y. Wu, Y. H. Chu, M. H. Wu, C. H. Hsu, H. Y. Lee, S. S. Sheu, W. C. Lo, and T. H. Hou, “A Comprehensive Modeling Framework for Ferroelectric Tunnel Junctions, ” in IEDM Tech. Dig., Dec. 2019. pp. 760-762.
[30] T. Y. Wu, H. H. Huang, Y. H. Chu, C. C. Chang, M. H. Wu, C. H. Hsu, C. T. Wu, M. C. Wu, W. W. Wu, T. S. Chang, H. Y. Lee, S. S. Sheu, W. C. Lo, and T. H. Hou, “Sub-nA Low-Current HZO Ferroelectric Tunnel Junction for High-Performance and Accurate Deep Learning Acceleration, ” in IEDM Tech. Dig., Dec. 2019. pp. 119-121.
[31] S. J. Kim, J. Mohan, H. S. Kim, J. Lee, C. D. Young, L. Colombo, S. R. Summerfelt, T. San, and J. Kim, “Low-voltage operation and high endurance of 5-nm ferroelectric Hf0.5Zr0.5O2 capacitors, ” Applied Physics Letters, vol. 113, 2018, Art. no. 182903,
[32] S. Salahuddin, and S. Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices, ”Nano Letters, vol. 8, no. 2, pp. 405-410, 2008.
[33] K. Ni, S. Jeffrey, Y. Huacheng, G. Benjamin, G. Bruce Rayner, Andrew Kummel, and Suman Datta “A Novel Ferroelectric Superlattice Based Multi-LevelCell Non-Volatile Memory, ” in IEDM Tech. Dig., Dec. 2019. pp. 699-672.
[34] J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger, J. Sundqvist, P. Kücher, T. Mikolajick, and L. Frey, “Ferroelectric Zr0.5Hf0.5O2 Thin Films for Nonvolatile Memory Applications, ’’ Applied Physics Letters, vol. 99, iss. 11, pp. 112901, 2011.