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研究生: 劉永宗
Yung-Tsung Liu
論文名稱: 下世代軟性薄膜電晶體與積體電路之熱傳模擬及其製程研究
The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation
指導教授: 李敏鴻
Lee, Min-Hung
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 76
中文關鍵詞: 非晶矽軟性薄膜電晶體三維積體電路
英文關鍵詞: Flexible a-Si:H TFT, 3D-IC
論文種類: 學術論文
相關次數: 點閱:119下載:6
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  • 在本世紀中,薄膜電晶體(TFT)和積體電路(IC)已被廣泛地研發,以不同的結構應用在電子相關設計方面。在這些研究之中,熱管理技術在元件的製程及在驅動時必須被列入考慮並且是影響元件特性的關鍵點。熱累積效應將會導致元件製程的失敗及元件特性下降。因此我們提出熱效應改善方法並且利用ISE TCAD半導體模擬軟體得到相關溫度分布圖形來驗證。第一章我們先簡介非晶矽軟性薄膜電晶體的發展變化沿革以及近年來3D立體積體電路(3D-ICs)的不同製程,並進一步探討研究動機和論文架構。第二章利用ISE TCAD模擬來驗證非晶矽軟性薄膜電晶體結構中夾一層熱傳導層,如銅、鋁、鉬,在偏壓驅動時可有效的逸散熱並且降低元件的溫度。第三章我們首先提出在3D-IC的不同層元件之間的隔絕氧化層中加入一層銅作為熱傳導層的結構,接著再利用ISE TCAD模擬2D模型在雷射誘發磊晶成長(LEG)製程時的溫度分布圖形。第四章我們將提出金氧半場效電晶體(MOSFET)的製程研究,在此製程步驟中,微影技術(Lithography)僅定義一道光罩。最後介紹元件製作的相關儀器操作流程與原理說明,以及Via陣列光罩圖形的設計。第五章對本論文之研究做結論並且探討未來研究工作目標與展望。

    In this century, thin film transistors (TFTs) and integrated circuits (ICs) have been developed extensively and used in many electronics applications and designs with a range of different structures. Among these research, thermal management would be considered and played a critical role when devices during operation or in fabrication process. Thermal accumulation effects may lead to failure in manufacturing process and devices performance degradation. Therefore, we propose thermal improvement for these conditions and utilize ISE TCAD simulation to obtain the temperature distribution and profile. In chapter 1, we first introduce the course of change and development for flexible a-Si:H thin-film transistor and recent three-dimensional integrated circuits (3D-ICs) fabrication. Furthermore, motivation and organization of thesis will be explored. In chapter 2, we utilize TCAD simulation to verify that flexible a-Si:H TFT with thermal conduction layer such as copper (Cu), aluminum (Al), molybdenum (Mo) can efficient to dissipate more heat and lower device temperature during bias stress operation. In chapter 3, we first propose one structure, which has a thermal conduction layer such as Cu in ILD oxide layer for monolithic 3D-ICs. Then TCAD simulation was performed by solving the temperature distribution for 2D model during laser-induced epitaxial growth (LEG) process. In chapter 4, we make a description of fabrication process for Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) by lithography technique with only one mask definition. The operating instructions, principle of related instruments and design of mask pattern for Via arrays also be later summarized. In chapter 5, at the end of this thesis, we will make conclusions and future works.

    Contents Related Publications…………………………………………………………………………i Abstract (Chinese)………………………………………………………………………….. ii Abstract………………………………………………………………………………………iii Acknowledge (Chinese)……………………………………………………………………...iv Contents….................................................................................................................................v Chapter 1 Introduction…........................................................................................................1 1.1 Overview of a-Si:H Thin-Film Transistor (a-Si:H TFT) on Flexible Substrate……...1 1.2 Recent Three-Dimensional Integrated Circuits (3D-ICs) Fabrication……………….3 1.2.1 Sequential Process……………………………………………………………….3 1.2.2 Wafer Bonding Process………………………………………………….............5 1.3 Motivation……………………………………………………………………………6 1.4 Organization of Thesis……………………………………………………………….7 Chapter 2 Simulation of Thermal Improvement for a-Si:H TFTs on Flexible Substrate……………………………………………………………………...……………….9 2.1 Thermal Conductivity…………….………………………………………………….9 2.2 The Structure of a-Si:H TFTs with Thermal Improvement on Flexible Substrate…12 2.3 Device Simulation …………………………………………………….....................15 2.3.1 DOS Model for the a-Si:H……………………………………………………...15 2.3.2 Thermodynamic Model for the Device Simulation…………………………….17 2.3.3 Major Physical Model………………………………………………………….18 2.4 Device Modeling and Results……………………………………………………….21 2.4.1 a-Si:H TFT with Different Substrates………………………………………….21 2.4.2 a-Si:H TFT with Thermal Conduction Layer on Flexible Substrate………..….31 2.5 Summary……………………………………………………………………………42 Chapter 3 Simulation of Thermal Accumulation Improvement for Fabrication Manufacturing of Monolithic 3D Integrated Circuits……………………………………43 3.1 The Structure for Thermal Accumulation Improvement in LEG Process for 3D-ICs …………………………………………………………………………………………..43 3.2 Device Modeling and Results……………………………………………………….46 3.3 Summary……………………………………………………………………………56 Chapter 4 Fabrication Process of One Mask MOSFET and Via Hole Design for 3D-IC Applications..………………………………………………………………………………..57 4.1 One Mask MOSFET Fabrication Flow……………………………………………..57 4.2 Process Principles…………………………………………………………………...60 4.2.1 Wafer Cleaning and Wet Etching………………………………………………60 4.2.2 Deposition Process and Thermal Annealing…………………………………...63 4.2.3 Lithography Process……………………………………………………………65 4.3 Design of Via Interconnect for 3D-IC Applications……………………..…………68 Chapter 5 Conclusions and Future Works………………………………………………..70 5.1 Summary…………………………………………………………………………70 References…………………………………………………………………………………...71

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