簡易檢索 / 詳目顯示

研究生: 洪敏惠
論文名稱: 先進矽鍺元件之應力估算與效能分析
Stress estimation and performance analysis of advanced SiGe devices
指導教授: 劉傳璽
Liu, Chuan-Hsi
李昌駿
Lee, Chang-Chun
學位類別: 碩士
Master
系所名稱: 機電工程學系
Department of Mechatronic Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 83
中文關鍵詞: 有限元素分析矽鍺合金延伸閘極寬度變異數分析
英文關鍵詞: Finite element analysis (FEA), SiGe stressor, extended poly gate width, ANOVA
論文種類: 學術論文
相關次數: 點閱:229下載:11
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 隨電子產品輕薄短小及功能多樣化之潮流,傳統之矽基半導體元件已無法符合下一世代元件於速度或功能之要求,因此除藉由縮減元件特徵尺寸外,應變工程之導入對於奈微電子元件之效能提升益顯重要。然而,電路圖案化之影響諸如具突起之多晶矽閘極對窄通道元件之引致應力大小,相關文獻卻鮮少有完整地討論。
    有鑑於此,本研究系統性地探討應變工程對於突出之多晶矽閘極寬度於具窄通道之P型半導體元件之性能表現。本論文分為兩部份,首先使用因子實驗設計概念結合有限元素之模擬法,對PMOS半導體元件進行應力模擬。分析時選擇四個重要設計因子,分別為延伸閘極寬度、源∕汲極長度、元件通道寬度,以及CESL內含應力值進行變異數分析,並討論其對於載子遷移率之影響性。由變異數分析可得知其因子重要影響程度前三項依序為CESL之應力值、CESL應力值與延伸閘極寬度兩因子間之交互作用,延伸閘極寬度。由上述分析獲知,延伸閘極寬度這一設計因子對於半導體元件其載子遷移率增益之影響為十分重要。其次,為了瞭解CESL應力與延伸閘極寬度兩因子間之交互作用關係,故於本研究使用中央合成設計法得到該因子間之反應曲面圖。藉由該曲面圖吾人可以進而獲得其優化之組合關係。
    第二部份,由於在文獻中可得知矽鍺合金源/汲極長度愈長則P型半導體元件其阻值會隨之減少。因此對不同大小之延伸閘極寬度與矽鍺合金之源/汲極長度進行敏感度分析,討論元件不同方向其應力值與載子遷移率之增益。分析結果指出當延伸閘極寬度於0.2 m時,其所貢獻之載子遷移率為最大。

    With the trend of multi-function and minimizing volume, traditional silicon-based semiconductor transistors have not met the performance requirements of next-generation devices. Consequently, in addition to diminish
    the characteristic sizes of nano-scale transistors, an introduction of advanced strained engineering is significant to enhance their performances. However,
    effects of pattern layouts such as different width of extended poly gate on narrow channel width on P-type metal oxide semiconductor field (PMOSFETs) has little reported as well as discussed completely.
    For this reason, this investigation analyzes PMOSFETs with a combination of a narrow gate length and extended poly width by using three dimensional finite element simulations integrated with the concept of factorial design of experiments. In the first part of this thesis, four design factors, including extended poly width, source/drain length, gate length, and the magnitude of
    CESL stressor, are selected to perform the analysis of variance (ANOVA) to confirm the interpretation and significance of effects for mobility gain of devices. The ANOVA results indicate that the effect importance is CESL
    stressor, interaction between CESL stressor and extended poly gate width, and extend poly gate width in sequence. From the above-mentioned results, it is found that extended poly width plays an important role for the mobility
    enhancement of devices. Moreover, for the purpose of investigating the interaction between CESL stressor and extended poly gate width, the central composite design is utilized to construct the contour of response surface.
    Subsequently, the better combinations of the factors are suggested in this thesis.
    In the second part, the sensitive analysis of stress effects within Si channel and corresponding mobility gains under the considerations of extended poly gate width and silicon germanium alloy embedded in the source/drain (S/D) region is implemented. The results point out that the mobility gain is maximum as the extended poly width is equal to 0.2 m.

    第一章 緒論 ............................................... 1 1.1應變矽發展 ............................................. 1 1.2 本論文研究方向 ........................................ 1 第二章 文獻探討 ............................................ 3 2.1 金氧半場效電晶體........................................ 3 2.2 金氧半場效電晶體之結構與特性 ............................ 4 2.3 金氧半場效電晶體之工作原理 .............................. 6 2.4 應變矽 ............................................... 7 2.5 全區域應變矽 ......................................... 12 2.6 區域應變矽 ........................................... 16 2.6.1區域應變矽在源/汲極 ............................... .. 16 2.6.2氮化矽覆蓋層 ........................................ 23 2.7應變矽的製程考量 ....................................... 28 2.8應變矽之載子遷移率計算 ................................. 28 第三章 實驗設計 ........................................... 31 3.1 前言 ................................................ 31 3.2 模擬步驟流程圖 ....................................... 31 3.3 因子設計與變數分析 .................................... 32 3.3.1反應曲面法 .......................................... 33 3.3.2最陡上升法或最陡下降法 ............................... 35 3.3.3中心合成設計 ........................................ 36 3.3.4 Box Behnken Design ................................ 37 3.3.5其他反應曲面設計 ..................................... 38 3.4 有限元素設計法........................................ 39 3.5 模擬材料之元素特性與性質 ............................... 44 3.6 模擬材料之參數設定 .................................... 44 3.6.1接觸蝕刻停止層 ...................................... 44 3.6.2矽鍺合金 ............................................ 45 3.7 建立有限元素模型 ...................................... 47 3.8 設定邊界條件 ......................................... 49 3.9半導體模型之驗證........................................ 50 第四章 結果與討論 ........................................ 54 4.1 變異數分析 ........................................... 54 4.2 反應曲面法 ........................................... 59 4.3 探討延伸閘極寬度與源/汲極長度對半導體元件的影響 .......... 65 4.3.1探討CESL壓應力對半導體元件的影響 ...................... 67 4.3.2探討矽鍺合金的源∕汲極對半導體元件的影響 ................ 71 4.3.3探討矽鍺合金源∕汲極與CESL的壓應力元件的影響 ............ 73 第五章 結論與未來展望 ..................................... 76 5.1因子設計與變析 ........................................ 76 5.2探討延伸閘極寬度與源/汲極長度對半導體元件的影響 ........... 77 5.2.1探討CESL壓應力對半導體元件的影響 ...................... 77 5.2.2探討矽鍺合金的源∕汲極對半導體元件的影響 ............... 78 5.2.3探討矽鍺合金源∕汲極與CESL的壓應力對元件的影響 .... 78 5.3 未來展望 ............................................. 78 參考文獻 ................................................ 80 表目錄 表2-1 n-MOSFET與p-MOSFET之比較表 ......................................................... 6 表2-2不同方向之張應力影響對於半導體元件的表現 .................................... 11 表2-3利用壓阻係數計算各種壓力對電子與電洞的遷移率增益 .................... 12 表2-4在不同的氣體流量比例,所得到的CESL應力值 ................................ 24 表2-5在三個不同方向之低應力其壓阻係數 .................................................... 30 表3-1兩個因子的變異數分析變異數分析表 .................................................... 33 表3-2比較3D自由網格和3D映射網格的優缺點........................................... 48 表4-1各因子的高水準和低水準組合 ................................................................ 55 表4-2 24矩陣之因子設計 ..................................................................................... 56 表4-3前三個重要效應因子組合之ANOVA 分析表格 ....................................... 58 表4-4中央合成設計法設計之23矩陣 ................................................................ 61 表4-5中央合成設計法反應因子二次模型的變異數分析表格 ........................ 62 表4-6配置模型方程式與模擬的點間的誤差值 ................................................ 64 vii 圖目錄 圖2-1 未來幾年的電晶體尺寸預測 ..................................................................... 3 圖2-2 金氧半電容 ................................................................................................. 4 圖2-3 n通道金氧半場效電晶體元件之結構圖 ................................................ 5 圖2-4 矽鍺虛擬基板長在矽通道下方 ................................................................. 8 圖2-5 電子在受到單軸的壓力應變的導電帶能谷 ............................................. 8 圖2-6 電洞在受到單軸的壓力應變後的能帶圖與等能面圖 ............................. 9 圖2-7 (a)左圖,為受力後其能股之分佈圖(b)能帶分裂之關係圖 .................. 9 圖2-8 在源/汲極使用矽鍺合金其半導體元件模型示意圖,小圖描述晶格在水平和垂直其應力分布 ........................................................................... 10 圖2-9 P-MOSFET應變矽其半導體元件之結構圖 ......................................... 12 圖2-10在鍺濃度各為0.1、0.22和0.29其長通道之有效電洞遷移率 ........... 14 圖2-11應變矽元件在鍺濃度各為0.1、0.22和0.29下其在短通道之轉移電導 ............................................................................................................... 14 圖2-12全區域應變矽的結構與能帶圖,電子通道(a)矽鍺表面(b)埋在矽鍺上 ................................................................................................................... 15 圖2-13三個材料的轉移電導圖(通道長度為10μm,通道寬度為21μm),三個Vt約為-0.2V .................................................................................... 16 圖2-14源/汲極重填矽鍺合金其步驟示意圖 ..................................................... 17 圖2-15在半導體元件中施加CESL壓應力和源/汲極使用矽鍺合金其Ion/ Ioff曲線圖 ....................................................................................................... 18 圖2-16使用壓組係數來推估模擬結果其載子遷移率增益與文獻資料之趨勢曲線比較圖 ............................................................................................... 18 圖2-17顯示不同的鍺含量對於通道的水平分量和垂直分量的應力值曲線(a) 顯示垂直分量的X方向的應力值(b)為水平分量的X方向的應力值 19 viii 圖2-18 應變異質接面的磊晶生長與鬆弛之晶格示意圖 .................................. 20 圖2-19 P 型電晶體之半導體元件結構模型 ....................................................... 21 圖2-20 不同的元件通道寬度之應力曲線圖 ...................................................... 22 圖2-21 不同元件通道寬度其電流增益曲線圖 .................................................. 22 圖2-22 氮化矽蝕刻停止層(CESL)對通道的張力方向表示 .............................. 24 圖2-23 不同的閘極高度對X 軸的應力影響 ..................................................... 25 圖2-24 將CESL 分為頂部、側邊和底邊這三個區塊其半導體模型示意圖, 通道長度為X 方向,寬度為Y 方向 ..................................................... 25 圖2-25 在長通道之下其Z 方向對不同區塊之模擬應力分佈 .......................... 26 圖2-26 不同區塊在不同閘極長度下其對元件通道X 方向之應力曲線圖 ..... 26 圖2-27 不同區塊在不同閘極長度下其對元件通道Y 方向之應力曲線圖 ..... 27 圖2-28 不同區塊在不同閘極長度下其對元件通道Z 方向之應力曲線圖 ...... 27 圖2-29電阻係數與晶體方向的關係 (a) 11 (b) 12 (c) 11 12 44      .......... 29 圖3-1 實驗設計模擬之流程圖 ........................................................................... 31 圖3-2 一階反應曲面和最陡上升路徑 ............................................................... 35 圖3-3 二因子之中央合成設計法 ....................................................................... 36 圖3-4 三因子的Box-Behnken 設計 ................................................................... 37 圖3-5 兩個變數的六角形等半徑設計 ............................................................... 38 圖3-6 一維軸向的有限元素網格 ....................................................................... 39 圖3-7 元素外力與位移方向定義 ....................................................................... 41 圖3-8 一階求節點之數學運算方法:疊代法 ...................................................... 42 圖3-9 一階求節點之數學運算方法:牛頓法 ..................................................... 42 圖3-10 一階求節點之數學運算方法:割線法 .................................................... 43 圖3-11 應變異質接面的磊晶生長與鬆弛示意圖 .............................................. 45 圖3-12 應變矽在矽鍺層上應變的表現 (拉力) .................................................. 46 ix 圖3-13左圖為矽(Si),右圖為矽與鍺(Ge)的混晶比 ...................................... 46 圖3-14建立有限元素模型 .................................................................................. 49 圖3-15文獻中模擬PMOS建造出3D模型 ....................................................... 50 圖3-16模擬驗證文獻中對於不同元件通道厚度其應力值 .............................. 51 圖3-17半導體元件之顯影示意圖 ...................................................................... 52 圖3-18有限元素應力模擬分析:為此實驗應力模擬模型之上視簡圖 ............. 52 圖3-19應力模擬模型之半導體結構圖 .............................................................. 53 圖4-1 MOSFET元件之俯視圖 ............................................................................ 55 圖4-2 延伸的多晶矽閘極寬度(A)與源∕汲極長度(B)以及CESL的應力值(D)三設計因子之立方體圖: 觀測效應值為載子遷移率增量 ................. 57 圖4-3因子效應的常態機率分佈圖:因子對於載子遷移率之效應重要性 .... 57 圖4-4二因子之中央合成設計法 ........................................................................ 60 圖4-5 CESL應力值與延伸的閘極寬度兩因子間作用對於載子遷移率增益的等高線圖 ................................................................................................... 62 圖4-6 CESL應力值與延伸的閘極寬度兩因子間作用對於載子遷移率增益的反應曲面圖 ............................................................................................... 63 圖4-7有限元素應力模擬分析:上圖為此實驗應力模擬模型之上視簡圖,下圖為結構圖 ............................................................................................... 66 圖4-8 2 GPa的CESL壓應力在不同的源∕汲極長度下的應力曲線變化...... 68 圖4-9 2 GPa的CESL壓應力在不同的源∕汲極長度下的載子遷移率增益變化 ............................................................................................................... 68 圖4-10 2 GPa的CESL壓應力的應力分佈圖 .................................................... 69 圖4-11 在半導體元件中使用2GPa之CESL壓應力之其模擬其不同延伸之閘極寬度其受表示其受力示圖…………………………………………...70 圖4-12鍺濃度25%的矽鍺合金於不同源∕汲極長度下之應力曲線變化圖 .. 72 圖4-13鍺濃度25%的矽鍺合金於不同的源∕汲極長度下之載子遷移率增益曲線圖 ....................................................................................................... 72 圖4-14鍺濃度25%的矽鍺合金和-2 GPa的CESL在不同的延伸閘極寬度下的應力曲線 ............................................................................................... 74 圖4-15鍺濃度25%的矽鍺合金和-2 GPa的CESL在不同的延伸閘極寬度下的載子遷移率增益 ................................................................................... 74 圖4-16鍺濃度25%的矽鍺合金和-2GPa的CESL在Y方向的應力分布圖 ..... 75

    [1] 劉傳璽,陳進來, 半導體物理元件與製程-理論與實務,五南出版社,2006。
    [2] G. D. Wilk, R. Mallace and J. M. Anthony, “High-k gate dielectrics: current status and materials properties considerations”, Journal of Applied Physics, vol. 89, pp. 5243-5275, 2001.
    [3] G. E. Moore, “Cramming more components onto integrated circuits”, Proceedings of the IEEE, vol. 86, pp. 82-85, 1998.
    [4] 鄭晃忠,劉傳璽,新世代積體電路製程技術,東華書局,2011。
    [5] K. Rim, S. Koester, M. Hargrove, J. Chu, P.M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill and H. S. P. Wong, “Strained-Si NMOSFETs for high-performance CMOS technology”, Symposium on VLSI Technology, pp. 59-60, 2001.
    [6] 劉恩科,朱秉升,羅晉生,半導體物理學,電子工業出版社,2006。
    [7] K. Rim, R. Anderson, D. Boyd, F. Cardone, K. Chan, H. Chen, S. Christansen, J. Chua, K. Jenkins, T. Kanarsky, S. Koester, B. H. Lee, K. Lee, V. Mazzeo, A. Mocuta, D. Mocuta, P. M. Mooney, P. Oldiges, J. Ott, P. Ronsheim, R. Roy, A. Steegen, M. Yang, H. Zhu, M. Ieong and H. S. P. Wong, “Strained Si CMOS (SS CMOS) technology: opportunities and challenges”, Solid State Electronics, vol. 47, pp. 1133-1139, 2003.
    [8] Y. C. Yeo, Q. Lu, T. J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro and J. Sakai, , “Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium”, International Electron Devices Meeting, pp. 753-756, 2000.
    - 81 -
    [9] Y. C. Yeo and J. Sun, “Finite-element study of strain distribution in transistor with silicon-germanium source and drain regions”, Applied Physics Letters, vol. 86, pp. 023103-1-023103-3, 2005.
    [10] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo and C. Hu, “Process-strained-Si (PSS) CMOS technology featuring 3-D strain engineering”, International Electron Devices Meeting, pp. 73-76, 2003.
    [11] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr and Y. E. Mansy, “A 90-nm logic technology featuring strained-silicon”, IEEE Transactions on Electron Devices, vol. 51, pp. 1790-1797, 2004.
    [12] K. Rim, J. Welser, J. L. Hoyt and J. F. Gibbons, “Enhanced hole mobilities in surface-channel strained-Si pMOSFETs”, International Electron Devices Meeting, pp. 517-520, 1995.
    [13] J. Welser, J. L. Hoyt and J. F. Gibbons, “Electron mobility enhancement in strained-Si N-type metal-oxide-semiconductor field-effect transistors”, IEEE Electron Device Letters, vol. 15, pp.100-102, 1994.
    [14] L. Washington, F. Nouri, S. Thirupapuliyur, G. Eneman, P. Verheyen, V. Moroz, L. Smith, X. Xu, M. Kawaguchi, T. Huang, K. Ahmed, M. Balseanu, L. Q. Xia, M. Shen, Y. Kim, R. Rooyackers, K. D. Meyer and R. Schreutelkamp, “pMOSFET with 200% mobility enhancement induced by
    - 82 -
    multiple stressors”, IEEE Electron Device Letters, vol. 27, pp. 511-513 2006.
    [15] 林宏年,呂嘉裕,林鴻志,黃調元,局部與全面形變矽通道 (strained Si channel)互補式金氧半 (CMOS)材料、製程與元件特性分析(I),奈米通訊, vol. 12, pp. 44-49, 2002。
    [16] J. Wu and X. Wang, “Stress engineering for 32nm CMOS technology node”, Solid State and Integrated Circuit Technology, pp. 113-116, 2008.
    [17] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh and T. Horiuchi, “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design”, International Electron Devices Meeting, pp. 247-250, 2000.
    [18] S. Pidin, T. Mori, R. Nakamura, T. Saiki, R. Tanabe, S. Satoh, M. Kase, K. Hashimoto and T. Sugii, “MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node”, Symposium on VLSI Technology, pp. 54-55, 2004.
    [19] S. Orain, V. Fiori, D. Villanueva, A. Dray and C. Ortolland, “Method for managing the stress due to the strained nitride capping layer in MOS transistors”, IEEE Transactions on Electron Devices, vol. 54, pp. 814-821, 2007. [20] S. E. Thompson, S. Suthram, Y. Sun, G. Sun, S. Parthasarathy, M. Chu and T. Nishida, “Future of strained Si/semiconductors in nanoscale MOSFETs”, International Electron Devices Meeting, pp. 1-4, 2006.
    [21] Montgomery,Design and analysis of experiments,三版,實驗設計與分析,黎正中,高立圖書,2010。
    - 83 -
    [22] 劉晉奇、褚晴暉,有限元素分析與ANSYS的工程應用,蒼海書局, 2005。 [23] 康淵,陳信吉,ANSYS入門,全華出版社,2008。
    [24] K. N. Chiang, C. H Chang and C. T. Peng, “Local-strain effects in Si/SiGe/Si islands on oxide”, Applied Physics Letters, vol. 87, pp. 191901-1 - 191901-3, 2005.
    [25] N. Yasutakea, A. Azumaa, T. Ishidaa, K. Ohuchia, N. Aokia, N. Kusunokia, S. Morib, I. Mizushimab, T. Morookaa, S. Kawanakaa and Y. Toyoshima, “A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond”, Solid State Electronics, vol. 51, pp. 1437-1443, 2007.
    [26] P. W. Liu, W. T. Chiang, Y. T. Huang, T. L. Tsai, C. H. Tsai, C. T. Tsai and G. H. Ma, “Improved layout dependence in high performance SiGe channel CMOSFETs”, Symposium on VLSI Technology, pp. 161-162, 2008.
    [27] 黃弘一,混合訊號積體電路佈局與分析課程講義,2003。

    下載圖示
    QR CODE