研究生: |
蔡元傑 Yuan-Chieh Tsai |
---|---|
論文名稱: |
脈衝式電鍍CuInSe2在抗反射結構基板之薄膜型太陽能電池研製 Development of absorbed layer on anti-reflection substrate by pulse voltage electrodeposition for CuInSe2 thin film solar cell |
指導教授: |
楊啟榮
Yang, Chii-Rong 楊希文 Yang, His-Wen |
學位類別: |
碩士 Master |
系所名稱: |
機電工程學系 Department of Mechatronic Engineering |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 中文 |
論文頁數: | 111 |
中文關鍵詞: | 銅銦化二硒 、脈衝式電鍍 、非硒化 、薄膜型太陽能電池 |
英文關鍵詞: | CuInSe2, CIS, pulse voltage electrodeposition, non-selenization, thin film solar cell |
論文種類: | 學術論文 |
相關次數: | 點閱:446 下載:7 |
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本研究利用脈衝式電壓電化學沉積法,結合非硒化熱處理製程,製造二硒化銅銦(CuInSe2,簡稱CIS)薄膜,並製造上蓋板結構(Superstrate),與下基板結構(Substrate)之CIS薄膜型太陽能電池,其結構分別為Glass/ITO/ZnO/CIS/Mo與Glass/Mo/CIS/ZnO/ITO。除CIS吸收層薄膜為脈衝式電壓電化學沉積法外,其餘透明導電層700 nm之ITO薄膜、50 nm之緩衝層ZnO與厚度為1 m背電極Mo,皆是利用射頻磁控濺鍍機台沉積。
本研究利用KOH濕式蝕刻技術,蝕刻<100>方向之單晶矽,形成倒金字塔陣列的抗反射結構,再使用SIGA製程(Silizium-Mikrostruktur, Galvanoformun, Abformung, SIGA),電鑄鎳鈷合金膜仁,成功製作出底部大小為45×45 m2,深度約30m之倒金字塔結構陣列,可用來熱壓低轉化溫度(glass transition temperature, Tg)玻璃基板,形成抗反射結構。
本研究成功由脈衝式電壓電鍍參數、鹽酸濃度與三乙醇胺(Triethanolamine, TEA)螯合劑濃度中,找出適合本研究非硒化熱處理製程之CIS薄膜,在ITO接觸電極基板上,其最佳化參數:三乙醇胺濃度1.0 M,鹽酸濃度0.845 M,Voff與Von分別為-0.4 V與-0.8 V,工作週期(duty cycle)選用50 %,電鍍時間320秒;在鉬背電極基板上之最佳參數:三乙醇胺濃度0.7 M,鹽酸濃度0.56 M,Voff與Von分別為0 V與-0.8 V,工作週期同樣選用50 %,電鍍時間600秒。
本研究為了使用非硒化爐熱處理製程,故將熱處理前之CIS吸收層成分比例,Cu:In:Se調整為1:1:5,並利用鹽酸濃度的調配與熱處理氣體選擇,將鍍層含氧量降至5 %以下,成功克服了一般電鍍製程中,鍍層含氧量偏高之現象。其最佳熱處理參數為使用7 %氫與93 %氬混和氣體,在200 °C
溫度下進行1.5小時之再結晶製程。最後得到薄膜成分Cu:In:Se比例約為1:1:2,此時CIS薄膜呈現類花椰菜之黃銅礦(Chalcopyrite)結構,其結晶顆粒大小約為1.5 m至2 m。
This study fabricated CuInSe2 layer by electrodeposition and non-selenization for CuInSe2, also called CIS, thin film solar cells, and compared the substrate and superstrate whose structure are Glass/Mo/CIS/ZnO/ITO and Glass/ITO/ZnO/CIS/Mo. Exception for CIS layers were produced by pulse voltage electrodeposition, other layers of solar cells, such as 700 nm ITO for contact electrodes, 50 nm ZnO for buffer layers, and 1 m Mo for back electrodes, were fabricated by RF sputtering.
We used KOH to etch <100> silicon wafers for arrayed inversed pyramids structure which can be an anti-reflection structure for monocrystalline silicon solar cells. We used this etched wafer whose bottom area of pyramids are 45×45 m2,30m in depth, to fabricate a Ni-Co mold by SIGA process( Silizium-Mikrostruktur, Galvanoformun, Abformung, also called SIGA) for hot embossing the low transition temperature, Tg, glasses of CIS solar cells as anti-reflection substrates.
For CIS layer, we successfully tuned the parameters of TEA, HCl, and other settings in pulse voltage electrodeposition. For ITO contact electrodes, the best parameters are 1.0 M TEA, 0.845 M HCl, -0.4 V for Voff, -0.8 V for Voff, 50% for duty cycle, and electrodeposited for 320 seconds. For Mo back electrodes, 0.7 M TEA, 0.56 M HCl, 0 V for Voff, -0.8 V for Voff, 50% for duty cycle, electrodeposited for 600 seconds.
To avoid selenization process, we adjusted the composition ratios of Cu:In:Se in CIS layer as 1:1:5, and used concentration of HCl and ambient gas of heat treatment to reduce the oxygen content of CIS layers to 5 %. The best heat treatment was 200 °C for 1.5 hours in 7% H2 and 93% Ar mixed gas. As the result, we could get the composition ratio of Cu:In:Se are 1:1:2, the crystalline are about 1 to 1.5 m.
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