現今CMOS工業正朝著「微小化」的趨勢向前邁進，而為了突破
摩爾定律的物理極限，於是在本實驗中先改善應用在記憶體上控制元
件的結構與製程條件，接著再改善穿隧場效電晶體以達到摩爾定律。
本實驗在一開始先利用模擬來尋求n/p/n bi-direction diode 最佳
化的結構與製程條件，然後製作出元件並使之廣泛的應用於記憶體結
構上，接下來將發展異質接面電晶體(BJT)如 金屬/介電質/金屬或金
屬/半導體/金屬的結構，與記憶體控制元件結合；接著經由實驗証實
高介電值/金屬閘極置於最後一步製程並應用在p 型的穿隧場效電晶
體，並發現在不同結晶方向的基板上對圓型元件的影響。最後討論p
型的穿隧場效電晶體在同樣高介電值/金屬閘極與同結晶方向(110)機
板上，高濃度鍺參雜與純矽的不同，並且在結晶方向(110)上不同電流
方向所造成的影響。

In order to follow Moore’s law and beyond the physical limitation, the trend of CMOS industry is developing toward scaling down. Therefore, the technology of stackable memory devices and advanced FET had been studied in this work.
In order to optimize the bi-direction devices, we used TCAD simulator for the process and structure design, as well as the M/I/M and M/S/M prepared. The HKMG p-TFET had been demonstrated for advanced FET with the gate last process. We also discuss the mechanism of the substrate orientation and anisotropic effect on ON-current of SiGe (110). The G-FET has been design and prepare for high performance FET with Tunneling mechanism.

[1] F. Pellizzer, et al., “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications,” in VLSI Tech. Digest of Tech Papers, pp.
122-123, 2006.
[2] F. Pellizzer, et al., “Novel Trench Phase-Change Memory Cell for Embedded and Stand-Alone Non-Volatile Memory Applications,” in VLSI Tech. Digest of Tech
Papers, pp. 18-19, 2004.
[3] G. Atwood, et al., “Current Status of Chalcogenide Phase Change Memory,”Device Research Conference (DRC), pp. 29-33, 2005.
[4] Woo Young Choi, et al., “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec,” IEEE Electron Device Letters (EDL), 28, p. 743, 2007.
[5] Tejas Krishnamohan, Donghyun Kim, et al., “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60mV/dec Subthreshold Slope,” IEEE International Electron Devices Meeting
Technical Digest (IEDM), p. 947, 2008.
[6] Saurabh Mookerjea, et al., “Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications,” Device Research Conference (DRC), p. 47, 2008.
[7] Peng-Fei Guo, et al., ” Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current,” IEEE Electron Device Letters (EDL), 30, p. 981,
2009.
[8] K. Bhuwalka, et al., “P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths,” Jap. J. Appl. Phys., 45(4B), pp. 3106-3109, 2006.
[9] H.Tanaka, et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” in VLSI. Tech. Dig., pp. 14-15,2007.
[10] Katsumata, et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices” , in VLSI. Tech.
Dig., pp. 136 – 137,2009.
[11] Jaehoon Jang, et al., “Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory” ,in VLSI. Tech. Dig., pp. 192 – 193, 2009.
[12] Jiyoung Kim, et al., “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive),” in VLSI. tech. Dig., pp.186-187,2009
[13] F. Pellizzer, et al., “Novel Trench Phase-Change Memory Cell for Embedded and Stand-Alone Non-Volatile Memory Applications,” in VLSI Tech. Digest of Tech
Papers, pp. 18-19, 2004.
[14] Hang Hu, et al., “MIM Capacitors Using Atomic-Layer-Deposited High-k (HfO2)1-x(Al2O3)x Dielectrics,” Electron Device Letters, Vol. 24, No. 2, Feb 2003
[15] Jung-Min Park, et al., “Mass Production Worthy MIM Capacitor On Gate polysilicon(MIM-COG) Structure using HfO2/HfOXCYNz/HfO2 Dielectric for Analog/RF/Mixed Signal Application,” IEEE International Electron Devices Meeting
Technical Digest (IEDM), p. 993 – 996, 2007
[16] Shengdong Zhang, et al., “A Novel Self-Aligned Bidirectional MIM Diode with Transparent Junctions for AM-LCD’s,” IEEE Electron Device Letters (EDL), Vol. 19,
No. 6, June 1998
[17] Tingkai Li, Sheng Teng Hsu,US. Patent No:2009/0032817
[18] Sheng Teng Hsu, Tingkai Li,US. Patent:7303971,2007
[19] W. Y. Choi, et al., “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec,” IEEE Electron Device Letters (EDL), Vol. 28, No. 8, Aug, 2007.
[20] D. Leonelli, et al., “Multiple-Gate Tunneling Field Effect Transistors with sub-60mV/dec Subthreshold Slope,” IEEE Solid State Devices and Materials (SSDM),pp. 767-768, 2009.
[21] J. Appenzeller, et al., “Band-to-band tunneling in carbon nanotube field-effect transistors,” Phys. Rev. Lett., vol. 93, no. 19, pp. 196805-1-4, 2004.
[22] P.-F. Wang, et al., “Complementary tunneling transistor for low power application,” IEEE Solid State Devices and Materials (SSDM), vol. 48, pp. 2281-2286,
2004.
[23] K. Bhuwalka, et al., “Vertical Tunnel Field-Effect Transistor,” IEEE Electron Device Letters (EDL), vol. 51, no. 2, pp. 279-282, 2004.
[24] H. G. Virani, et al., “Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs,” IEEE
Solid State Devices and Materials (SSDM), pp. 384-385, 2009.
[25] M. Sterkel, et al., “Characteristics and Optimization of Vertical, and Planar Tunneling-FETs,” Journal of Applied Physics (JAP), pp. 15-18, 2005.
[26] S. H. Kim, et al., “Germanium-Source Tunnel Field Effect Transistors with Record High ION/IOFF,” in VLSI Tech. Dig., pp. 178-179, 2009.
[27] Y. Taur, et al., “25 nm CMOS design considerations,” IEEE International Electron Devices Meeting Technical Digest (IEDM), pp. 789-792, 1998. [28] Peng-Fei Guo, et al., “Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current,” IEEE Electron Device Letters (EDL), p. 981, 2009.
[29] C.-Y. Yuan, et al., “Hole mobility enhancement of Si0.2Ge0.8 quantum well channel on Si,” Applied Physics Letters (APL), 90, 012114, 2007.
[30] S. Maikap, et al., “High-K HfO2/TiO2/HfO2 multilayer quantum well flash memory devices,” SST, 22, pp. 324-347, 2007.
[31] J. C. Bean, et al., “Ge, Si, Si strained-layer superlattice grown by molecular beam epitaxy, ” J. Vue. Sci. Tech. A, vol. 2 no. 2, pp. 436-440, 1984.
[32] M. H. Liao, et al., ” An Investigation about the Limitation of Strained-Si Technology,” Applied Physics Letters (APL), 013105, 2008.
[33] P. Butcher, et al., “Dependence of peak current density on acceptor concentration in germanium tunnel diodes,” IEEE Solid State Devices and Materials (SSDM), vol. 3. pp. 358-359. 1962.
[34] Woo Young Choi, et al., “70-nm Impact-Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs),” IEEE
International Electron Devices Meeting Technical Digest (IEDM), p. 955, 2005.
[35] M. Born, et al., “Tunnel FET: A CMOS device for wide temperature range,”MIEL, p. 124, 2006.
[36] F. Mayer, et al., “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance,” IEEE International Electron Devices Meeting
Technical Digest (IEDM), p. 163, 2008.
[37] Chenming Hu, et al., “Green Transistor -A VDD Scaling Path for Future Low Power ICs,” in VLSI. Tech. Dig., pp. 14-15, 2008.