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研究生: 李惠雅
Hui-Ya Li
論文名稱: 以FPGA實現基於部分距離搜尋法之競爭式學習系統
FPGA Implementation of Competitive Learning with Partial Distance Search
指導教授: 黃文吉
Hwang, Wen-Jyi
學位類別: 碩士
Master
系所名稱: 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 中文
論文頁數: 53
中文關鍵詞: 競爭式學習FPGA
英文關鍵詞: competitive learning, FPGA
論文種類: 學術論文
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  • 本論文針對k贏家通吃競爭式學習法之場域可程式化閘陣列(FPGA)實作提出一新演算法。k個得以進行更新的獲勝神經元,為每一個輸入向量在小波域(wavelet domain)中執行部分距離搜尋(partial distance search)所找出的最近似者。在大多數的應用裡,PDS以軟體方式被用於神經元搜尋的加速。此章節將提出一個適於硬體實現的新PDS演算法。此演算法使用子空間搜尋(subspace search)、有限精度計算(finite precision calculation)、多係數累積(multiple-coefficient accumulation)、和查表式除法(lookup-table based division)等技巧來有效降低面積複雜度與運算延遲。也提出ㄧ個新的排序架構,用於PDS步驟後k個獲勝神經元的判定。
    在此提出的硬體架構將以專用邏輯區塊電路(custom logic block)的方式內嵌於Nios軟核心中央處理器的算術邏輯單元(ALU)中。Nios處理器所提供的客製指令(custom instruction)便是用於存取專用邏輯區塊電路的方式。我們已測量出,Nios軟核心中央處理器執行用於「k贏家通吃競爭式學習訓練」之部分距離搜尋程式客制指令所需的CPU時間。實驗結果顯示CPU時間低於未搭配部份距離搜尋硬體電路的Pentium IV處理器。

    This paper presents a novel algorithm for the field programmable gate array (FPGA) realization of the competitive learning (CL) algorithm with k-winners-take-all activation. The k winning neurons for updating are those best matching the input vector in the wavelet domain with partial distance search (PDS). In most applications, the PDS is adopted as a software approach for attaining moderate codeword search acceleration. In this chapter, a novel PDS algorithm well-suited for hardware realization is proposed. The algorithm employs subspace search, finite precision calculation, multiple-coefficient accumulation, and lookup-table based division techniques for the effective reduction of the area complexity and computation latency. A novel sorting architecture is also proposed for identifying the k winning neurons after the PDS process.
    The proposed implementation has been adopted as a custom logic block in the arithmetic logic unit (ALU) of the softcore NIOS processor. The custom instructions are also derived for accessing the custom logic block. The CPU time of the NIOS processor executing the PDS program with the custom instructions for k-winners-take-all CL training is measured. Experiment results show that the CPU time is lower than that of Pentium IV processors executing the PDS programs without the support of custom hardware.

    中文摘要 i Abstract ii 誌謝 iv 目 錄 v 附圖目錄 vii 附表目錄 viii 第一章 緒論 1 1.1 研究背景與動機目的 1 1.2 全文架構 6 第二章 基礎理論介紹 8 2.1 k贏家通吃競爭式學習法 8 2.2 離散小波轉換 9 2.3 部分距離神經元搜尋法 12 第三章 kCL架構與硬體實現 16 3.1 子空間搜尋(Subspace search) 17 3.2 有限精度計算(Finite precision calculation) 19 3.3 多係數部分距離累積(Multiple-coefficient partial distance accumulation) 20 3.4 排序電路 23 3.5 查表式除法(lookup-table based division) 26 3.6 子空間部分距離搜尋法硬體實現 28 3.7 kCL之VLSI硬體架構 31 3.8 軟硬體共同設計(Hardware/Software Codesign) 35 3.9 內嵌於軟核心處理器的PDS使用者自訂邏輯區塊 40 第四章 實驗數據與效能比較 43 第五章 結論 51 參考文獻 52

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