2000年10月美國政府機構NIST正式宣布選用Rijndael演算法作為AES、且於2001年成為美國聯邦資訊處理加密標準，逐步取代Data Encryption Standard（DES）成為新一代的加密標準。
　　本研究有別於128-bit、32-bit AES之資料路徑（Datapath），使用管線結構（Pipeline），可以達到每秒數十億位元（GBPS）之高產量（throughput）。在一些消費性電子如行動通訊、RFID上並不需要較大的資料傳輸速率，因此8-bit之資料路徑是個不錯的選擇。
在本論文中，使用FPGA來實現8-bit AES之硬體電路，以達到小面積及較高產率（throughput）之優點，以利於不同應用上。
本研究利用VHDL、Xilinx ISE 7.1、ModelSim來驗證與模擬。且使用不同硬體架構來實現並加以比較。其中使用Block RAM可以有效節省面積（本論文中指Slice之使用量）且可以提供不錯的產率（throughput）。

On 2000, the National Institute of Standards and Technology (NIST) announced that the Rijndael encryption algorithm was chosen as the Advanced Encryption Standard (AES), which would be the next generation of encryption standard to replace the Data Encryption Standard (DES), and became the federal information encryption standard the next year.
　　In our research, which is differ from other AES algorithm in data-path width of 128 bit or 32 bit that would probably pipelined to achieve high throughput like tens Giga Bit Per Second (GBPS). In fact, an 8 bit width data-path AES algorithm should be enough in some consuming electronic applications such as Radio Frequency Identification (RFID) which needs only a slower data transfer rate.
　　In this thesis, we implemented an 8 bit AES circuits on Field Programmable Gate Array (FPGA) and expected that it could be used in many different applications by its advantages of small area and more high through. More, the AES circuits were written in VHDL code by the designing tool of Xilinx ISE and verified and simulated by ModelSim. Moreover, by the way of using Block RAMs could reduce area (here is Slices utilization) effectively and provide a good throughput.

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