研究生: |
龔峻瑋 Jiun-Wei Gung |
---|---|
論文名稱: |
重置型積分器於內部模型原理之應用 Applications of a Reset Law to Internal Model Principle-Based Controller Design |
指導教授: |
呂有勝
Lu, Yu-Sheng |
學位類別: |
碩士 Master |
系所名稱: |
機電工程學系 Department of Mechatronic Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 113 |
中文關鍵詞: | 線性積分器 、內部模型原理 、滑動模式 、重置控制 |
英文關鍵詞: | Linear integrator, Internal model principle, Sliding mode, Reset control |
論文種類: | 學術論文 |
相關次數: | 點閱:217 下載:0 |
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一般控制器使用的積分器為線性積分器(Linear Integrator,LI),其易使系統響應有超越量(Overshoot)。重置型積分器是由J. C. Clegg所提出,故又稱為Clegg積分器(Clegg Integrator,CI)。將CI應用於積分控制器,當系統輸出誤差為零,便將積分器的輸出值歸零,如此可有效地降低響應的超越量。
以內部模型原理 (Internal Model Principle,IMP)為基礎的控制迴路包括干擾(Disturbance)的模型,可漸近地消除干擾影響;同樣地,若控制迴路包含參考訊號(Reference)的模型,則可漸近地達到完美的軌跡追蹤。但,由於控制迴路加入內部模型,常使得系統輸出響應有極大的超越量或振盪(Oscillation)現象。針對以內部模型原理為基礎的控制器加入CI,以降低系統輸出響應的超越量或振盪。並提出提前重置積分器,使暫態時保有CI降低超越量特性,且穩態時仍有LI抑制干擾的能力。
本論文將三菱伺服馬達與精密線性模組和量測元件等整合成一個線性平台系統,進行直線運動定位控制實驗。採用 TI TMS320C6713 DSP與 Xilinx可程式閘陣列(FPGA)結合而成之控制器硬體核心,並以C語言與硬體描述語言(VHDL)作為控制器設計之發展工具,並將所提出的控制律實現與驗證於伺服馬達平台,以驗證其可行性。
Commonly-used liner integrator (LI) usually causes system overshoot. J. C. Clegg proposed a reset control element, called Clegg integrator (CI). The CI consists of an integrator whose output is set to zero whenever its input is zero, which can effectively reduce the maximum overshoot in output response.
The internal model principle (IMP) states that when a control loop contains a disturbance model, the system can eliminate disturbance asymptotically. Similarly, when a control loop contains the model of a reference signal, the system can achieve prefect reference tracking. However, a control system designed nased on IMP usually gives output responses with great overshoot or oscillation. The CI with advance reset is added to the IMP-based control system in order to improve transient performance without sacrificing its capability of disturbance rejection.
Experimental studies are conducted on a linear motion stage for positioning control. In the experimental system, the control kernel is a DSP/FPGA system, and the C language and VHDL are utilized as development tools for the servo control system. Experimental results demonstrate the effectiveness of the proposed reset law.
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