簡易檢索 / 詳目顯示

研究生: 范揚群
Fan, Yang-Chun
論文名稱: 一種驗證先進三閘極電晶體幾何變異之理論與實驗方法
A New Theory and Its Experimental Verifications of Geometric Variation in Advanced Trigate FinFETs
指導教授: 劉傳璽
Liu, Chuan-Hsi
莊紹勳
Chung, Shao-Shiun
學位類別: 碩士
Master
系所名稱: 機電工程學系
Department of Mechatronic Engineering
論文出版年: 2016
畢業學年度: 105
語文別: 中文
論文頁數: 72
中文關鍵詞: 邊線粗糙度線寬粗糙度表面粗糙度幾何變動率
英文關鍵詞: line edge roughness, line width roughness, surface roughness, geometric variations
DOI URL: https://doi.org/10.6345/NTNU202204675
論文種類: 學術論文
相關次數: 點閱:126下載:24
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 為了不斷的提高平面型金氧半場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET)的性能,藉由縮短通道長度以及降低氧化層厚度來達成汲極飽和電流(Id,sat)的提升,因此產生了許多問題,如短通道效應(short channel effect)、閘極漏電流(gate leakage)的產生等,使得發展出擁有更好之閘極控制能力的三閘極鰭式電晶體(trigate FinFET),卻又衍生出其鰭的高度提升下之幾何變動率(geometric variations)的問題。
    本論文發展出了對於三閘極電晶體上幾何變動率的理論,包括了線(line)以及表面粗糙度(surface roughness),而幾何變動率與氧化層厚度之變動率(oxide thickness variations)分別可由量測閘極電容與閘極電流得到,實驗結果顯示,三閘極電晶體在鰭的高度不斷提升下,受到了嚴重的幾何變動率的影響,其中氧化層表面粗糙度造成了介面缺陷的產生,以及電子遷移率的下降,進而導致提高了臨界電壓的變動率(Vth),此外線粗糙度分別由邊線粗糙度(line edge roughness)以及線寬粗糙度(line width roughness)所組成,而三閘極電晶體顯示出更嚴重的邊線粗糙度,造成較大之汲極電流之變動率(Id),並且發現於長通道中所引起的原因為蝕刻製程(etchant process)所致,於短通道中所引起的原因為不精確的曝光所致。這些研究成果,提供了一個具有量化且具有系統的研究方法,對於我們在未來對於三閘極電晶體設計及量產上,頗具參考價值。

    To improve the performance of MOSFET, the scaling of channel length and the oxide thickness will be able to increase the saturation current. But the additional problem including short channel and gate leakage are induced. On the other hand, trigate FinFET, which has a better gate controllability, creates another problem of geometric variations.
    A new theory has been developed for geometric variations, including not only line but also surface roughness, of trigate FinFETs. The geometric variation and oxide thickness variations can be measured from gate capacitance and current variations, respectively. Experimental results show that trigate devices are subject to serious geometric variations as the fin height scales up, among which surface roughness creates interface traps and induces mobility degradation, leading to a worse Vth variation. In addition, line roughness is decoupled into line-edge and line-width roughness. Trigate devices exhibit rough line edges, induced by etchant process in long-channel regime and by inaccurate lithography in short-channel regime, leading to larger drain-current variation. These results provide us a systematic and quantifiable approach to improve geometric variations in the design and manufacturing of future trigate devices.

    第一章 緒論 1.1 研究背景與動機…………………………………………..……………1 1.1.1 本論文之架構……………………...…………………………1 第二章 文獻回顧……………………………………………………………..…3 2.1 金氧半場效電晶體………………………………………………..……3 2.1.1 摩爾定律…………………………………………….………..3 2.1.2 電晶體之結構…………………………………….…………..3 2.1.3 電晶體之特性……………………………………….………..6 2.1.4 次臨界特性(Subthreshold characteristics)…………………...7 2.2 幾何變動(geometric variation)…...………………………………….....8 2.2.1 邊線粗糙度(LER)對於MOSFET的影響…………….….…..9 2.2.2 探討邊線粗糙度(LER)及隨機摻雜擾動(RDF)對於臨界電壓Vth的變動率…………….………………………..………….15 2.2.3 邊線粗糙度(LER)與線寬粗糙度(LWR)對於臨界尺度 下之變動率(Critical Dimension variation)………….………18 第三章 元件製備與實驗方法…………………………………………..….….27 3.1 元件製備………………………………………………………………27 3.2 實驗設備……...…………………………………………………….…28 3.3 實驗原理…………..……………………………………………….….29 3.3.1 邊線粗糙度之變動率(LRV)與表面粗糙度之變動率(SRV)之理論……………………………………………………..…...32 3.3.2 電荷汲引技術(charge pumping)……………………………36 第四章 結果與討論……………………………………………………………37 4.1 三閘極電晶體與平面型電晶體之幾何變動率之量測結果………....37 4.2 幾何變動率(geometric variation)於三閘極電晶體中之影響………..40 4.2.1 氧化層表面粗糙度(surface roughness variation, SR)對電晶體之影響…………………………………………………….41 4.2.2 氧化層之邊線粗糙度(LER)和線寬粗糙度(LWR)對於電晶體微縮下之影響…………………………………………….44 4.2.3 邊線粗糙度(LER) 對於源極(source)與汲極(drain)端之影響程度及原因之探討………………………………………….46 4.2.4 探討通道長度於閘極電流變動率與閘極電容變動率之影響…………………………………………………………….49 4.2.5 預測氧化層厚度變動率(σTox)與氧化層面積變動率(σA)與電場之相對關係…………………………………………….53 4.3 氧化層之幾何變動率對於電晶體之電性的影響……………………55 4.3.1 氧化層之幾何變動所造成臨界電壓之變動(σVth)………...55 4.3.2 氧化層之幾何變動率對於電晶體關閉時漏電流之變動率的影響………………………………………………………….58 4.3.3 探討氧化層之幾何變動率對於汲極電流的影響………….60 4.4 平面型與三閘極電晶體之氧化層變動率所造成電路上的影響……64 4.4.1 利用直流電壓(DC)進行量測反向器之特性圖………….…64 4.4.2 利用脈衝(pulse)了解幾何變動率所造成其RC delay的嚴重程度……………………………….……………….65 第五章 結論與未來展望………………………………………………………68 5.1 結論……………………………………………………………………68 5.2 未來展望………………………………………………………………69 參考文獻………………………………………………………………………..70 表目錄 表1 源極與汲極之相關因子………………………………………………48 表2 臨界電壓之變動率Vth的影響成分分析……………………………57 表3 汲極電流變動率之推導………………………………………………63 圖目錄 圖2-1 基本MOS結構圖………………………………………………………4 圖2-2 金氧半場效電晶體(MOSFET)之剖面結構圖………………………...5 圖2-3 n-MOSFET之ID-VD輸出特性圖………………………………………6 圖2-4 線邊緣粗糙度(LER)之示意圖………………………………………...9 圖2-5 從SEM之電流資料中萃取線邊緣粗糙度的波型…………………..10 圖2-6 兩個不同粗糙度之LER poly line,一個較小(左)一個較大(右)…….10 圖2-7 分別為不同wafer上之邊線緣與線寬度的RMS…………………….11 圖2-8 比較不同LER對於NMOS之Ioff-Ion影響……………………………12 圖2-9 比較不同LER對於PMOS之Ioff-Ion影響…………………………….12 圖2-10 閘極邊線粗糙度(LER)之示意圖…………………………………….13 圖2-11 S/D接面之摻雜輪廓示意圖………………………………………….14 圖2-12 熱退火前後之擴散比較圖……………………………………………14 圖2-13 二維模擬之各種Lc對於不同RMS的趨勢圖……………………..…15 圖2-14 在奈米尺度下,主要之內部變動因子………………………………..16 圖2-15 在元件微縮下,RDF所造成臨界電壓Vth的變動率…………………16 圖2-16 幾種製程在不同線寬下,所產生之LER的程度…………………….17 圖2-17 模擬LER的增加使得σVth大幅提高………………………………...17 圖2-18 LER/LWR線邊緣之模擬流程……………………………………......18 圖2-19 ξ=25 nm, α=0.5………………………………………………………..19 圖2-20 σ =1 nm, α=0.5………………………………………………………...19 圖2-21 σ=1 nm, ξ=25 nm……………………………………………………...20 圖2-22 CD=50 nm, σ=1 nm, α=0.5, ξ=25 nm…………………………………20 圖2-23 各種尺寸之臨界尺度下之變動率,(a)10 nm、(b)50 nm、(c)500 nm…21 圖2-24 RMSσ對於臨界尺度下之變動率的影響……………………………22 圖2-25 相關長度ξ對於臨界尺度下之變動率的影響………………………22 圖2-26 (a)為兩條LER與LWR之草圖,(b)為line edge 1之範例圖…………23 圖2-27 (a)SEM拍攝之實際圖(b)從SEM之拍攝圖中獲得之線條(c)利用auto-correlation function進行Gaussian fitting……………………….24 圖2-28 分別為不同製程下,平均LER和平均LWR之eff粗糙度………….25 圖2-29 相關參數之盒形圖………………………………………………….25 圖2-30 不同製程下的Fin/NW之ξ/Λeff ……………………………………...26 圖2-31 在不同微影圖案技術(pattering techniques)下之ξ/eff ……………...26 圖3-1 28 nm製程之多晶矽平面型COMS元件…………………………….27 圖3-2 28 nm製程之多晶矽三閘極CMOS元件…………………………….28 圖3-3 實驗設備及量測平台…………………………………………………29 圖3-4 氧化層薄膜之邊線粗糙度(LR)與表面粗糙度(SR)…………………30 圖3-5 氧化層薄膜表面粗糙度的變動(surface roughness variation)……….31 圖3-6 氧化層薄膜之邊線粗糙度(line edge/width roughness)……………...31 圖3-7 表面粗糙度變動率(surface roughness variation)之示意圖………….34 圖3-8 電荷汲引電流之量測方法……………………………………………36 圖4-1 平面型(上)與三閘極(下)電晶體之閘極電流分佈比較……………..38 圖4-2 平面型(下)與三閘極(上)電晶體之電容分佈比較…………………..38 圖4-3 σIg/Ig,avg與σCg/Cg,avg之比較圖其中(a)為平面型電晶體元件,(b)為鰭(fin)之高度為10 nm之三閘極電晶體元件,(c) 為鰭(fin)之高度為30 nm之三閘極電晶體元件……………………………………………..39 圖4-4 氧化層厚度變動率(σTox)之比較圖,鰭(fin)之高度為30 nm之元件擁有最大的σTox…………………………………………………………39 圖4-5 閘極面積變動率(σA)之比較圖,圖中顯示鰭(fin)高度為30 nm之元件擁有最大之σA…………………………………………………40 圖4-6 幾何變動之樹狀圖……………………………………………………41 圖4-7 氧化層表面粗糙度程度(σSR)表示圖………………………………..42 圖4-8 三閘極電晶體之電子遷移率比較圖…………………………………43 圖4-9 表面粗糙度引起較多的接面缺陷(interface traps)…………………..43 圖4-10 邊線粗糙度(LER)與線寬粗糙度(LWR)示意圖……………………..45 圖4-11 隨通道縮減,邊線粗糙度(LER)與線寬粗糙度(LWR)之成分分析圖………………………………………………………………………46 圖4-12 閘極到源極Cgs與閘極到汲極Cgd之電容示意圖……………………47 圖4-13 源極與汲極端之邊線粗糙度比較示意圖……………………………48 圖4-14 源極與汲極端的邊線粗糙度之相依程度……………………………49 圖4-15 量測於V_gs-V_th=0之低功率(low power, LP)時,通道縮減對於其閘極電流變動率之成分的影響…………………………………………51 圖4-16 量測於V_gs-V_th=1之高功率(high power, HP)時,通道縮減對於其閘極電容變動率之成分的影響…………………………………………52 圖4-17 氧化層面積之變動率(σA)對於電場之預測…………………………54 圖4-18 氧化層厚度之變動率(σTox)與電場之預測………………………….54 圖4-19 氧化層之幾何變動率對於臨界電壓之變動率Vth的影響…………56 圖4-20 臨界電壓變動率之成分分析…………………………………………58 圖4-21 幾何變動所造成電晶體關閉時之電流來源………………………....59 圖4-22 量測源極端(source)電流與電晶體關閉時之電流(Ioff)之相依性…...59 圖4-23 量測閘極端(gate)電流與電晶體關閉時之電流(Ioff)之相依性……...60 圖4-24 平面型電晶體的汲極端飽和電流圖(Id,sat)的變動率………………...61 圖4-25 三閘極電晶體的汲極端飽和電流圖(Id,sat)的變動率………………...61 圖4-26 平面型(下)與三閘極(上)電晶體之汲極電流變動率Id比較.………62 圖4-27 平面型電晶體與三閘極電晶體之汲極電流之變動率分析…………63 圖4-28 反向器(inverter)之電路示意圖………………………………………64 圖4-29 直流電壓(DC)的反向器轉移特性曲線之變動率Vout……………...65 圖4-30 暫態(transient)之輸出波形…………………………………………...66 圖4-31 延遲時間之變動率(στ)比較………………………………………….67

    [2-1] G. Moore, “Cramming more Components onto Integrated Circuits,” in IEEE Electronics, p. 114, 1965.
    [2-2] 劉傳璽,陳進來,第三版,半導體物理元件與製程-理論與實務,五南文化出版社,2006。
    [2-3] E. R. Hsieh, S. S. Chung, C. H. Tsai, R. M. Huang, C. T. Tsai, et al., “A Novel and Direct Experimental Observation of the Discrete Dopant Effect in Ultra-Scaled CMOS Devices,” in IEEE Very Large Scale Integration Technology Digest, pp. 194-195, 2011.
    [2-4] E. R. Hsieh, E. D. Wang, S. S. Chung, “A New Variation Plot to Examine the Interfacial-Dipole Induced Workfunction Variation in Advanced High-k Metal-Gate CMOS Devices,” in IEEE Very Large Scale Integration Technology Digest, p. 204, 2016.
    [2-5] E. R. Hsieh, Y. L. Tsai, S. S. Chung, C. H. Tsai, R. M. Huang, et al., “The Understanding of Multi-Level RTN in Trigate MOSFETs through the 2D Profiling of Traps and Its Impact on SRAM Performance: A New Failure Mechanism Found,” in IEEE International Electron Devices Meeting, pp. 19.2.1-19.2.4, 2012.
    [2-6] H. M. Tsai, E. R. Hsieh, S. S. Chung, C. H. Tsai, R. M. Huang, et al., “The Understanding of the Trap Induced Variation in Bulk Tri-gate Devices by a Novel Random Trap Profiling (RTP) Technique,” in IEEE VLSI Technology Digest, pp. 189-190, 2012.
    [2-7] A. Asenov, S. Kaya, and A. R. Brown, “Intrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness,” IEEE Transactions on Electron Devices, Vol. 50, pp. 1254-1260, 2003.
    [2-8] E. R. Hsieh, S. T. Lin, S. S. Chung, R. M. Huang, C. T Tsai, et al., “Gate Current Variation: A New Theory and Practice on Investigating the Off-State Leakage of Trigate MOSFETs and the Power Dissipation of SRAM,” in IEEE International Electron Devices Meeting, pp. 31.2.1-31.2.4, 2013.
    [2-9] D. Reid, C. Millar, S. Roy, and A. Asenov, “Understanding LER-Induced MOSFET VT Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples,” IEEE Transactions on Electron Devices, Vol. 57, pp. 2801-2807, 2010.
    [2-10] S. Xiong, J. Bokor, Q. Xiang, P. Fisher, I. Dudley, P. Rao, H. Wang, and B. En, “Is Gate Line Edge Roughness a First-Order Issue in Affecting the Performance of Deep Sub-Micro Bulk MOSFET Devices?,” IEEE Transactions on Semiconductor Manufacturing, Vol. 17, 2004.
    [2-11] S. Xiong, J. Bokor, Q. Xiang, P. Fisher, I. Dudley, and P. Rao, “Study of Gate Line Edge Roughness Effects in 50 nm Bulk MOSFET Devices,” in Proc. SPIE, Vol. 4689, pp. 733-741, 2002.
    [2-12] S. Xiong, J. Bokor, “A Simulation Study of Gate Line Edge Roughness Effects on Doping Profiles of Short-Channel MOSFET Devices,” IEEE Transactions on Electron Devices, Vol. 51, 2004.
    [2-13] Y. Ye, F. Liu, and M. Chen, “Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness,” IEEE Transactions on Very Large Scale Integration System, Vol. 19, 2011.
    [2-14] F. Zhao, Q. Wang, L. Zhang, and Z. Jiang, “Impact of Line Edge Roughness and Line Width Roughness on Critical Dimension Variation,” IEEE International Conference, Vol. 3, pp. 475-479, 2012.
    [2-15] X. Jiang, R. Wang, T. Yu, J. Chen, and R. Huang, “Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I–Modeling and Simulation Method,” IEEE Transactions on Electron Devices, pp. 3669-3675, 2013.
    [2-16] R. Wang, X. Jiang, T. Yu, J. Fan, J. Chen, D. Z. Pan, and R. Huang, “Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability,” IEEE Transactions on Electron Devices, pp. 3676-3682, 2013.
    [3-1] M. Koh, W. Mizubayashi, K. Iwamoto, H. Murakami, T. Ono, M. Tsuno, T. Mihara, K. Shibahara, S. Miyazaki, and M. Hirose, “Limit of Gate Oxide Thickness Scaling in MOSFETs due to Apparent Threshold Voltage Fluctuation Induced by Tunnel Leakage Current,” IEEE Transactions on Electron Devices, Vol. 48, pp. 259-264, 2001.
    [3-2] M. Depas, B. Vermeire, P. W. Mertens, R. L. V. Meirhaeghe, and M. M. Heyns, “Determination of Tunnelling Parameters in Ultra-Thin Oxide Layer Poly-Si/SiO2/Si Structures,” Solid-State Electronics, Vol. 38, pp. 1465-1471, 1995.
    [3-3] M. Cassé, X. Garros, O. Weber, F. Andrieu, G. Reimbold, and F. Boulanger, “Study of N-induced Traps due to Nitrided Metal Gate in HK/MG nMOSFETs,” Proceedings of the European Solid State Device Research Conference, pp. 325-328, 2010.

    下載圖示
    QR CODE